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viterbi_for_bch.rar
- Viterbi based trellis decoder for (7,4) - binary BCH code,Viterbi based trellis decoder for (7,4)- binary BCH code
nonsystem
- Generate trellis data of a rate-1/n convolutional encoder.卷积码1/n的编码器，注意生成的是非系统码。-Generate trellis data of a rate-1/n convolutional encoder. Convolutional codes 1/n of the encoder, the attention generated by the non-system code.
98_1099
- Viterbi, Trellis and Turbo Code implementation on a next-generation DSP
Viterbi_check
- It is a verilog code for viterbi decoding with trellis diagram
TCM
- Trellis coded modulation(TCM) VHDL code
RAM_BLOCK
- Ram block code in Verilog