是Turbo码交织器的VHDL设计与仿真的文献-Is the Turbo Code Interleaver Design and Simulation of VHDL literature

Turbo code simulation. This code can be compiled on all platforms. The interleaver size is 10000. SNR can be varied according to user s need. However, each time SNR is changed, the code must be recompiled.-Turbo code simulation. This code