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多路选择器
- 由3-mux和4-mux组成12-mux的verilog编码
mux
- 多路选择器 verilog CPLD EPM1270 源代码-MUX source verilog CPLDEPM1270
Mars_EP1C6F_Fundermental_demo(Verilog)
- FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and multiplier, such as MUX.
veriloghdl
- 多路选择器（MUX）verilog hdl 多路选择器（MUX）verilog hdl-MUX (MUX) verilog hdl multiplexer (MUX) verilog hdl
4x1_mux
- verilog code for 481 mux
mux
- the multiplexer program are designed 2:1 and 4:1 in verilog model
Desktop
- 用verilog HDL编写的多路选择器的代码，包括一部分延迟-Prepared using verilog HDL code MUX, including part of the delay
verilogcode
- Verilog语言实现的多路选择器和移位寄存器的源代码.-Verilog language implementation of MUX and the shift register the source code.
SRAM_interface
- PSRAM 和flash接口的verilog实现。-Numonyx M18 SCSP StrataFlash with PSRAM interface ( AD-Mux)。
4x1_mux
- this a simple Verilog source code for 4X1 mux.-this is a simple Verilog source code for 4X1 mux.
verilog-programs
- These are first programs of my asic and fpgas lab.This folder contains simple half adder and its test bench using verilog language.Then it also contains 4 to 1 mux using two 2 to 1 muxes.Then its also has its test bench to check the code.These progra
3bit-Wide-5to1-Mux
- 3bit Wide 5to1 Mux by verilog
verilog-code
- 都是verilog代码：多路选择器代码，储存器代码，时钟分频器代码，串并转换电路代码，香农扩展运算代码，ram代码。-MUX code and REGISTER code clock divider code string conversion circuit code, Shannon extended op code, the ram code.
8-1-mux
- 八选一数据选择器，Verilog HDL语言描述，包含文件说明和波形截图-8-1 MUX, Verilog HDL language descr iption ， contains the file descr iption and waveform capture
mux
- 使用VERILOG實現多工器之設計,並附上tb供測試-VERILOG realized using multiplexer design, along with tb for testing
verilog-source-codes
- the attached programs are source codes of 4-bit ring counter, 16x1 mux, 8x3 priority encoder, 4x16 decoder, full subtractor using two half subtractors
mux
- verilog code it is about multiplexer
Mux
- Multiplexer on verilog
mux_2to1_4to1_8to1
- design verilog hdl for mux 2to1, mux4to1, mux8to1
mux_with multiplier
- mux to use with adder with full adder and half adder