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8051-core
- 8051单片机是一种应用最广泛的单片机.它的内核设计非常精简,这是用Verilog硬件描述语言写的8051单片机内核-8051 is a most widely used SCM. Its kernel design has been streamlined, This is used Verilog hardware descr iption language to write the 8051 microcontroller core
verilog_cpu
- 一个小单片机的verilog源代码, 包含说明文档-a small SCM verilog source code contains documentation
adc
- 编写verilog代码 利用实验箱上的A/D芯片完成模数转换。输入电压由实验箱提供，其幅值在0~5V间变化，由电位器控制。输出信号显示输入的模拟电压值，由数码管显示为2位BCD码的形式。
ads7822
- 利用Verilog语言实现读取ADS7822模数转换芯片的串行输出数据-it is convinient for us to use A/D converter to get digital data
TFTDriverNew_V2
- TFT液晶屏驱动模块Verilog源码。实现方法：XC95288+K6R4008，K6R4008主要用作帧缓冲区，此模块仅支持256色-TFT LCD driver module Verilog source code. Realization: XC95288+ K6R4008, K6R4008 mainly used as a frame buffer, this module only supports 256 colors
Verilog
- Verilog经典参考书籍，为周立功公司为了方便国内读者学习Verilog而写的一本详尽的参考书。-Classic Verilog reference books for the week of meritorious service for the convenience of domestic companies to learn Verilog reader written a detailed reference book.
spi
- 三线spi接口，用verilog实现，作为一个模块，可以接收并行数据，然后串行发送-Three Line spi interface, using Verilog implementation, as a module, can receive parallel data, and then send the serial
verilog_examples
- 一些自己编写的verilog代码，供初学者学习用，觉得还是合适的。-I have written a number of Verilog code, for beginners to learn, think it appropriate.
sgs32
- Verlog HDL 写得一款32路方波发生器，例子是4路可以自己加，相位可调，频率可调，占空比可调。具体参见readme.doc.此处只提供了源码包含顶层模块sgs32.v 子模块dds.v和pll设置模块altp.v及波形驱动文件-Verlog HDL write a 32 square-wave generator, for example, is able to add 4-way, phase adjustable, adjustable frequency, adjustable d
answer
- 用verilog编写的抢答器程序。由硬件思维编写，由一个多路开关和一个触发器构成，比起c，简单并且稳定。-Answer written by Verilog program. Prepared by the hardware of thinking, by a multi-way switch and a flip-flop structure, compared to c, simple and stable.
Verilog_PS2
- ps2控制的verilog代码，学习的好资料-ps2 control Verilog code, a good study information
16bit_display8bitLED
- Abstract七段显示器在DE2可当成Verilog的console，做为16进位的输出结果。Introduction使用环境：Quartus II 7.2 SP1 + DE2(Cyclone II EP2C35F627C6)简单的使用switch当成2进位输入，并用8位数的七段显示器显示16进位的结果。-Abstract Seven-Segment Display as Verilog to DE2 at the console, as 16 of the output binary. In
key1
- 用verilog硬件描述语言写的一个LED的程序，可以用到各种模块中，实用性很强，欢迎大家下载使用。-Verilog hardware descr iption language used to write procedures for a LED can be used in a variety of modules are very practical, and welcome to download.
rsic
- 这是我同学在上海交大实习的时候做的一个单片机的verilog代码实现，希望对大家有帮助-This is my internship students of National Chiao Tung University in Shanghai to do when a single chip verilog code, and they hope to help you
jishu60
- verilog实例，用verilog模块例化方式设计一个60S的定时器。-verilog example verilog modules were used to design a way of timer 60S.
upload_code
- 每个代码见压缩包内文件名，分别为使用单片机控制AD9627的代码，已在硬件电路实现；基于FPGA的DDR SDRAM控制源代码，将文件夹内文件加入同一工程即可；以及三份FPGA内部学习资料。 C代码开发环境为KeilC，verilog代码开发环境为Quartus。 -See each code within the compressed package file name, respectively, for the use of the AD9627 single-chip contr
dds_var
- 自己写的一个简单的DDS控制器，此程序包包含完整的VERILOG写的程序，操作有点简单，输出正弦波，方波，锯齿波，通过键盘可以选择输出波形，与大家共享-To write a simple DDS controller, this package contains a complete program written in VERILOG, a bit simple to operate, the output sine wave, square wave, sawtooth, through t
miaobiao
- 用VERILOG实现秒表的开发设计，(1)熟悉按键扫描、按键防抖和数码管驱动接口电路原理；(2)掌握按键扫描、按键防抖和数码管驱动接口电路设计开发；(3)掌握状态机实际应用设计。-To achieve the development of a stopwatch with VERILOG Design, (1) be familiar with key scanning, image stabilization and digital control key driver interface c
eda
- 在Verilog HDL中使用任务（task）， 利用有限状态机进行时序逻辑的设计，利用SRAM设计一个LIFO(In Verilog HDL, the task (task) is used, the finite state machine is used to design the time series logic, and a LIFO is designed by SRAM)
verilog
- this is a file about a microprocessor en multiples sections