搜索资源列表
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高级链路层协议的实现，vhdl，fpga,- 8 bit parallel backend interface
- use external RX and TX clocks
- Start and end of frame pattern generation
- Start and end of frame pattern checking
- Idle pattern generation and detection (all ones)
- Idle pattern
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检测巴克码实现帧同步传输，vhdl语言，帧头,Detection of Barker code transmission to achieve frame synchronization
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光纤通信中的SDH数据帧解析及提取的vhdl实现源代码，共包含帧同步、E1及F1码流提取、DCC1码流提取、帧头开销串行输出四个主要模块-SDH fiber-optic communication data frame analysis and retrieval implementation of vhdl source code, include the frame synchronization, E1 and F1 stream extraction, DCC1 stream extra
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用vhdl语言编写的一个控制程序，主要功能是输入码同步，输出字和帧信号-vhdl language using a control program, the main function is to input code synchronization, and frame signals output word
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分析帧同步算法，提供帧同步的状态机实现图以及得到的正确仿真图形。-Analysis of frame synchronization algorithm, to provide frame synchronization state machine implementation plans and get the correct simulation graphics.
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巴克码发生器的vhdl程序，巴克码主要用于通信系统中的帧同步，便于与随机的数字详细相区别，易于识别。-Barker Code Generator vhdl program, Barker Code is mainly used for frame synchronization in communication systems, and the random number to facilitate more differentiated and easy identification.
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基于vhdl帧同步提取建模与设计 该设计主要是在一帧数据的前后插入巴克码-Based on vhdl frame synchronization extraction modeling and design
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帧同步的vhdl程序源代码，巴克码同步实现。-frame synchronization of the vhdl source code, Barker code synchronization
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ＦＰＧＡ在通信上的运用：基于vhdl的帧同步程序-Application of FPGA in communication: Based on vhdl frame synchronization procedures
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此程序为帧同步程序，采用状态机的vhdl描述方式编写。-This procedure for frame synchronization procedures, using the state machine to prepare the way vhdl descr iption.
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巴克码装到信息内同时将巴克码识别出来，实现帧同步的vhdl设计-Barker code loaded to the information identified while Barker code, vhdl design to achieve frame synchronization
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vhdl实现帧同步的巴克码器，含有移位寄存器，判决器、译码器。-vhdl realize frame synchronization barker code, contains a shift register, judgment, decoder.
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