搜索资源列表
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
CPU
- 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
The_design_of_MIPS_CPU(VHDL)
- MIPS CPU设计实例的完整文档，台湾一个大学生的MIPS CPU完整设计文档，内附设计代码。-a complete document of MIPS CPU design , a Taiwan university students complete MIPS CPU design document, containing the design code.
vhdl-MIPS
- Quartus-Altera Nios... VHDl based, complete MIPS implementation, document, flowcharts plus code
microprocessor
- 一个微处理器的Verilog代码，根据英文书籍《数字设计与架构》中的例子而写，能够运行MIPS指令，能正确执行跳转指令。通过modelsim仿真，含测试代码。-Verilog code for a microprocessor, according to the English book " Digital Design and Architecture" was written in the example, to run MIPS instructions to jump
single_cycle
- single cycle mips code in vhdl
mips-VHDL
- 自己作业代码，应用VHDL语言实现一个多周期的简单MIPS核-AlphaJob code, the application of VHDL language more than one cycle of a simple MIPS core
6_Sets_of_8051_VHDL_Verilog
- it has 6 packages of 8051 sources,including source code(VHDL and Verilog),dc scr ipts, pdfs, netlists etc. and a MIPS IP package
MIPSSYN
- MIPS vhdl code. 8 files in
mips_cpu_code_Rev_0.5
- vhdl MIPS CODE , WORKING GOOD
OpenMIPS_VHDL_study_v1.0
- 10天实现OPENMIPS处理器-VHDL版[内有详细代码，testbench和设计文档，十天教你学会MIPS架构CPU设计]-10 days to achieve the OPENMIPS processor-VHDL version [within a detailed code, testbench and design documents, ten days to teach you to learn MIPS architecture CPU design]
f32c-master
- FPGArduino源码，f32c：VHDL的MIPS和RISC-V指令集实现(FPGArduino source code, f32c:VHDL MIPS and RISC-V instruction set implementation)