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part2
- Implement a 3-digit BCD counter. Display the contents of the counter on the 7-segment displays, HEX2− 0. Derive a control signal, from the 50-MHz clock signal provided on the DE2 board, to increment the contents of the counter at one-se
Verilog_UDP
- 辛辛苦苦找到的UDP的资料,在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段,在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西,希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-de
VHDL
- 7段数码管译码器和8421码十进制计数器的程序-7 segment digital tube, and 8421 yards decimal decoder program counter
freqm
- a simple implementation of a frequency meter with the BCD-counter and the 7-segment LED display
04_dynamic_hex2
- This is 7-segment LED contoler in vhdl
VerilogHDL_code
- 几个常用的接口实验的程序代码,用Verilog HDL语言编写的,包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, I2C, marquees
7-segment
- VHDL Design of BCD to 7-segment decoder using PROM
rafal2
- VHDL project for FPGA SPartan 3 using IseWebpack 10.1. This is an implemetation of FSM for testing 7 segment with dot point 4 digit LED display.
qiduan
- 用vhdl语言实现按键操控多个七段码控制-Vhdl language with control buttons to control a number of Seven-Segment Code
Mars-EP1C6-F_code2
- 此包为FPGA学习板接口实验程序源代码,共包括13个实验程序,有7段数码管,1602液晶显示,12864液晶显示,I2C总线,串口通信,拨码开关等.-The packet interface to FPGA board experimental procedure to study the source code, a total of 13 experimental procedure, there are 7-segment digital tube, 1602 LCD 12864 LCD,
display
- vhdl,七段数码管驱动程序,完成数字显示功能-vhdl, seven-segment digital tube driver, complete the digital display
Seven-Segment-Decoder
- 用VHDL语言在FPGA上实现将十进制bcd码转换成七段led显示码-FPGA using VHDL language to achieve will be converted to decimal bcd yards led seven segment display code
verilog
- 通过I2C接口读写EEPROM 在本项目中,我们利用Verilog HDL实现了部分I2C总线功能,并能够通过该总线对AT24C02进行读写操作。为了便于观察读写eeprom的结果,我们将读写的数据同时显示在七段数码管上,并设定读写的数据从0到255不断循环,这样就可以方便进行比较。 -Through the I2C interface to read and write EEPROM in this project, we use Verilog HDL to achieve some o
digital_seven_segment_clock
- digital seven segment clock
bcd7seg
- A BCD to 7 segment circuit
wtut_edif
- Xilinx clock. DIGITAL CLOCK for Spartan-3 Starter Board. This design shows how to generate a digital clock and display the output to the multiplexed 7- segment display in VHDL.
xq_Test7
- VHDL语言编写一个BCD计数器并在七段显示数码管上显示的程序,实现了动态扫描,而且很好用-VHDL language a BCD counter and in the seven-segment display digital tube display process to achieve a dynamic scanning, and it just works
LED7s
- 用VHDL语言编写的 LED七段显示译码器-Written in VHDL language with the LED seven-segment display decoder
7segmentLED
- 7段数码管显示源代码。基于VHDL语言,实现对7段数码管显示。-7 segment LED display source code. Based on the VHDL language, achieving seven segment LED display.
VHDL-3BCD
- 3位BCD码的计数显示电路。BCD码计数电路从0计到9然后返回到0从新计数。3位BCD码计数器可以实现从0到999的十进制计数。要将计数过程用七段显示LED数码管显示出来,这里采用动态分时总线切换电路对数码管进行扫描,对数码管依次分时选中进行输出计数的个、十、百位的数据。-3 BCD code count display circuit. BCD code counting circuit count from 0 to 9 and then back to 0 from the new cou