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leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOT
yanshi.rar
- 给予VHDL的延时函数 是简单的开始时间的延时,VHDL delay to the start of the function is a simple time delay
CyclonePLL
- Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟
wtut_sc
- DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock
FPGA
- fpga时延与定时控制,描述了设计时的注意事项-FPGA time delay and timer control
DE2_Default
- 延时一个 时间通过QUARTUS环境编写VHDL代码-delay a time
Schmitt-trigger-keyboard-interface
- 基于施密特触发的键盘接口电路，有效降低触发延迟，缩短键盘反应时间 以verilog实现-Schmitt trigger on the keyboard interface circuit, effectively reducing the trigger delay and shorten the reaction time to verilog implementation keyboard
cordic
- we propose a low-cost sequential and high performance architecture for the implementation of CORDIC algorithm in two computation modes. It suited for serial operation that performs conversion between polar and rectangular coordinate systems, essentia
loop-HELLO
- 8位数码管循环显示HELLO.采用不同的延时时间，让数码管上HELLO,左右显示时的时间不同-8-bit digital control loop shown HELLO. With different delay time on the digital control HELLO, display different times around
light
- 城市十字交叉路口红绿灯控制系统主要负责控制东西走向和南北走向的红绿灯的状态和转换顺序，关键是各个状态之间的转换和进行适当的时间延时，基于以上考虑，采用如下设计： (1)当东西走向的绿灯亮时，南北走向的红灯亮，并保持25S (2)当东西走向的绿、黄灯亮时，南北走向的红灯亮，并保持5S (3)当东西走向的红灯亮时，南北走向的绿灯亮，并保持15S (4)当东西走向的红灯亮时，南北走向的绿、黄灯亮，并保持5S (5)最后又回到（1）状态，并周期重复进行。 -The city cr
The-question-of-time-delay
- 关于VHDL的时延问题的若干分析，可以借鉴-The analysie of time delay of Quartus II
design_4
- 利用48M时钟信号定时得到事先设置好的延时，通过延时信号接到蜂鸣器发出提示声音。主持人，抢中，抢答时间到，答题时间到，四个信号分别触发计数延时，最后把得到的三个报警信号相与（因为系统设置为低电平有效），作为最后的报警信号。 每个触发延时计时，在触发信号无效（‘1’）时，将计数值归零，触发信号有效时（‘0’），开始记时钟个数，记到一定（根据需要事先设置好）个数，就得到延时时间（延时时间=时钟个数*时钟周期），时间延时报警信号无效，得到一定时间的报警信号。 -48M clock signal t
2-to-4-Decoder-with--Configuration
- 2-to-4 Decoder with Testbench and Configuration This set of design units illustrates several features of the VHDL language including: Using generics to pass time delay values to design entities. Design hierarchy using instantiated components.
KEY_down_detect
- 按键检测VHDL程序，主要实现对开发板按键的检测以及一些时间延迟的信息。程序较全，可以按照不同的开发板设置相应的引脚进行操作。-Key detection VHDL program, the main achievement of some time delay detection and information on the development board keys. Than the whole program, you can set the corresponding pin to
P
- 该工程实现了BDPSK调制器的设计，其中的主要模块有差分编码模块、分频模块、延时模块等。该工程在Quartus软件下运行。-The project implements the design of BDPSK modulator, the main module has a differential coding module, frequency module, time delay module etc.. The operation of the project in Quartus so
watch_dog
- 基于EPM1270F256实现的4路看门狗控制逻辑，实现了滤波、延时、复位功能。-Based on EPM1270F256 4 road guard dog control logic, to realize the function of filtering, time delay and reset.
mingmie-V4.1
- Based on the time delay estimation of power spectrum, Based on piecewise nonlinear weight value Pso algorithm, Machine learning routines.
sa261
- Calculation crosshairs diffraction image at different distances, Including the generalized cross-correlation function GCC time delay estimation, PV modules contain, MPPT module, BOOST module, inverter module.
bb322
- Based on the time delay estimation of power spectrum, Various resource allocation algorithm, Matlab wavelet analysis on complex.
led
- 利用计数器设计延时函数，通过四个led灯的闪烁，可以直观观察延时时长，fpga器件cyclone iv LCMXO2-1200HC-4TG144CR1,在demo板上作简路图(Using the counter to design the delay function, through the flashing of four LED lights, we can observe the delay time directly, FPGA device cyclone IV LCMXO2-12