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Computer Architecture Handbook on Verilog HDL
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用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放
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基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), throu
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此实验例程适用于Actel Flash架构的ProASIC3/E系列FPGA，适合于FPGA及Verilog HDL的初学者，配套EasyFPGA030开发套件。-Routine application of this experiment in the Actel Flash architecture ProASIC3/E series FPGA, fit in the FPGA and Verilog HDL for beginners and supporting development
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This is a source code of 256 point fft architecture. This code is also available with opencores-This is a source code of 256 point fft architecture. This code is also available with opencores
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CAM is useful vhdl code to understand its architecture which helps to write any code
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a verilog code for booths multiplier has been uploaded, simple architecture.
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一个微处理器的Verilog代码，根据英文书籍《数字设计与架构》中的例子而写，能够运行MIPS指令，能正确执行跳转指令。通过modelsim仿真，含测试代码。-Verilog code for a microprocessor, according to the English book " Digital Design and Architecture" was written in the example, to run MIPS instructions to jump
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Verilog HDL code for implementation of double floating point architecture. Program takes care of diffent exceptions like overflow, underflow, NaN etc
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基于RISC结构的8位微处理器的verilog源代码，很好的东西。-8-bit RISC-based microprocessor architecture verilog source code, a good thing.
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this document explain the majors of VERILOG language in a very efficient and briefly manner.this is very useful to learn about hardware design and implementing them by FPGAs.
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MIPS体系结构用verilog实现的记分牌算法，标流水线-Architecture implemented using verilog scoreboard algorithm, standard line
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计算机组成实验作业1，fpga开发板，verilog语言编写-Composition of experimental computer operating 1, fpga development board, verilog language
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计算机组成实验作业2，fpga开发板，verilog语言编写-Composition of experimental work computer 2, fpga development board, verilog language
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计算机组成实验作业3，fpga开发板，verilog语言编写-Composition of experimental computer operating 3, fpga development board, verilog language
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计算机组成实验作业4，fpga开发板，verilog语言编写-Composition of experimental computer operating 4, fpga development board, verilog language
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计算机组成实验作业5，fpga开发板，verilog语言编写-Composition of experimental computer operating 5, fpga development board, verilog language
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计算机组成实验作业6，fpga开发板，verilog语言编写-Composition of experimental computer operating 6, fpga development board, verilog language
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MIPS is a reduced instruction set computer (RISC) instruction set architecture (ISA)[1]:A-1[2]:19 developed by MIPS Technologies (formerly MIPS Computer Systems). The early MIPS architectures were 32-bit, with 64-bit versions added later.
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The architecture greatly influenced later RISC architectures such as Alpha.
As of April 2017, MIPS processors are used in embedded systems such as residential gateways and routers.
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