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verilog source
- verilog的源代码。给出来常用的一些例程，对于verilog的使用和学习都有很大的帮助作用。-Verilog source code. Out to some routines commonly used for the use and Verilog study has been very helpful.
usbhostslave
- USB主机和设备的verilog代码，实现了USB1.1协议规范的要求-USB host and equipment Verilog code to achieve the USB 1.1 protocol specification requirements
CAN协议控制器的Verilog实现
- 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
pcit32_verilog_lattice
- 本文件是pci的verilog源代码程序-pci the Verilog source code procedures
verilogpll
- 用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
yunsuan-verilog
- 运算器的实现，即实验指导书中的实验一，文件中包含有原代码及端口设置（可变），用vrilog HDL编程，Xilinx ISE 6仿真，并在实际电路中得到实现．-operations for the realization of the experimental guidance of a book. document contains the original code and port settings (variable), with vrilog HDL programming, Xili
FPGA_test_frequency
- 本原码是基于Verilog HDL语言的FPGA原程序，主要用于测频率，特点主要是可以更快地测频。实时性更高。-primitive code is based on Verilog HDL FPGA original program, mainly for the measurement frequency, the main features can be faster frequency measurement. Real-time higher.
turbo[1].tar
- turbo码的verilog程序，有意者请下载。-turbo code verilog procedures Interested parties please download.
发一个基于ModelSim仿真的Verilog源代码包
- 发一个基于ModelSim仿真的Verilog源代码包-made a ModelSim simulation based on the Verilog source code
seqdet
- 对串行输入的数据流进行检测的ＶＥＲＩＬＯＧ源代码-On the serial input data streams to detect the Verilog source code
lcd_1602
- 1602 LCD控制的verilog代码，学习的好东西-1602 LCD control Verilog code, learning good things
4to1MUX
- Verilog code for 4 t0 1 multiplexer
ShiftRegister
- Shift register verilog code
DDS
- this a code for DDS in Verilog-this is a code for DDS in Verilog
Receiver
- 基于802.11a的OFDM基带硬件设计的verilog代码，在Xilinx ISE环境下实现-The OFDM-based 802.11a baseband hardware design of the verilog code, in the Xilinx ISE environment to achieve
motorrun
- This code is used to drive a unipolar stepper motor using SPARTAN3E FPGA. and coding is done in verilog
calculator
- EDA设计源代码，verilog计算器设计-EDA design source code, verilog calculator design
fen-pin-Verilog(2013-06-25-09.54.41)
- 任意小数分频，适用于对精确度要求不高的代码中-Any fractional divider, suitable for less demanding precision code
Altera-LVDS_IP
- 自己总结的Altera_LVDS的IP核的设计及仿真分析，已在实际工程中应用到，并且带有源代码和仿真代码，总结的文档，非常有用。(My summary of the Altera_LVDS IP kernel design and simulation analysis, has been applied in practical engineering, and with source code and simulation code, summary of the document, ver
FPGA_SOURCE_CODE
- ad9910 FPGA VERILOG 初始化代码，(Ad9910 FPGA VERILOG initialization code)