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CAN协议控制器的Verilog实现
- 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
verilogpll
- 用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
FPGA_test_frequency
- 本原码是基于Verilog HDL语言的FPGA原程序，主要用于测频率，特点主要是可以更快地测频。实时性更高。-primitive code is based on Verilog HDL FPGA original program, mainly for the measurement frequency, the main features can be faster frequency measurement. Real-time higher.
seven_seg
- 一个verilog代码，该代码很适合初学者熟悉FPGA的开发流程，主要功能为实现七段代码管的显示，主要针对xilinx公司spartan3系列的FPGA-a verilog code that are very suitable for beginners FPGA familiar with the development process, main function of the realization of the code in paragraph 107, xilinx against
seg7led
- 一个verilog写的控制LED的FPGA的代码。-Write a Verilog control LED of the FPGA code.
motorrun
- This code is used to drive a unipolar stepper motor using SPARTAN3E FPGA. and coding is done in verilog
FirmwareVerilog
- 测试USB2.0和FPGA通讯的程序，其中包括固件程序，VERILOG代码 上位机软件-USB2.0 and FPGA communications test procedure, including firmware, VERILOG code PC software
FPGA_SOURCE_CODE
- ad9910 FPGA VERILOG 初始化代码，(Ad9910 FPGA VERILOG initialization code)