搜索资源列表
FPGA_for_I2C
- i2c code for the verilog -i2c code for the Verilog
YCbCr_to_rgb
- 颜色空间转换代码,ycbcr对rgb的转换verilog代码.YCBCR的格式是ITU601格式.-color space conversion code, RS right rgb conversion Verilog code. YCBCR format is ITU601 format.
MedianFilter33
- 3*3 中值滤波的verilog代码实现，已经调试通过！欢迎提出宝贵意见！-3 * 3 filtering to achieve the verilog code has been adopted debugging! Welcomed the valuable advice!
DCTofJPEG
- 用verilog代码写的JPEG压缩核心模块DCT变换之蝶形单元算法-verilog code written using JPEG compression core module DCT's butterfly modules algorithm
VGAverilog
- VGA的控制方法的verilog代码，还不错！-VGA control of verilog code, quite good!
H264verilogcore
- H264的VERILOG代码,基本实现了全部的功能-H264 of the Verilog code, the basic realization of all the functions
syndetect
- 帧同步检测，verilog代码 是同步保护的经典范例-frame detection, verilog code
lcd-code
- 比较完整的LCD接口代码，verilog编写，分为6800和8080两种CPU接口，且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program
VGA
- 用VERILOG写的VGA显示代码，经本人调试确定可以正常运行-VERILOG written with VGA display code, as I confirmed to be the normal operation of debugging
verilog
- DSP_FPGA最新程序代码 verilog-DSP_FPGA latest Verilog code
H264
- h.264(verilog HDL) 这是基于流水线结构的H.264解码器源码-h.264 (verilog HDL) which is based on the pipeline structure of the H.264 decoder source code
DWT
- It s implementation on DWT. This was wrttend in verilog.
begin
- 9/7提升小波变换中奇偶分裂步、预测步、边界延拓处理和模块测试平台的Verilog代码描述：-9/7 lifting wavelet transform in odd and even split-step, prediction step, boundary extension process and module test platform described in Verilog code:
VerilogHDL
- 9/7提升小波变换中奇偶分裂步、预测步、边界延拓处理和模块测试平台的Verilog代码描述：-9/7 lifting wavelet transform in odd and even split-step, prediction step, boundary extension process and module test platform described in Verilog code:
cordic-code
- how to implement cordic algorithm via verilog
dvi-code-verilog
- dvi encoder and decoder for fpga
eDP
- eDP接口TFT-LCD显示驱动原码（verilog+c）-eDP Interface TFT-LCD display driver source code (verilog+c)
code-code
- spi，uart等接口的verilog代码和说明文档，能帮助大家了解总线的功能。-spi, uart verilog code and documentation, such as interfaces, can help you understand the function of the bus.
7_to_1-LVDS-dispaly-from-FLASH
- 该代码是基于verilog 实现的代码，可以用于对接受1080P的LVDS视频数据并处理后显示到各种规格的LCD屏幕上，且支持从FLASH中读取BMP的图片数据并实时显示到LCS屏幕-The code is based on the code verilog achieve, it can be used for receiving LVDS 1080P video and data processing displayed on a variety of LCD screen, and sup
DWT_verilog-code
- 图像压缩是图像处理中的一个重要课题，在减少图像尺寸以实时传输和存储方面起着非常重要的作用。许多标准推荐使用DWT进行图像压缩。DWT的计算复杂度对基于DWT的图像压缩算法的实时使用提出了重大挑战。在本文中，我们提出了一种改进的提升方案来计算近似和详细的DWT系数。修正的方程使用右移运算符和6位乘法器。计算中的层级减少到一个，从而最小化延迟和增加吞吐量。ViTEX-5 FPGA上实现的设计工作在180 MHz，功耗小于1W的功率。该设计占用了FPGA上不到1的LUT资源。所开发的体系结构适合于FP