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Code_for_MedianFilter33.rar
- 3x3中值滤波器的FPGA实现(VERILOG),3x3 median filter FPGA implementation (VERILOG)
Implementation-of-SIFT-detection
- 摘要：针对SIFT 特征提取的硬件实现结构复杂、难以达到实时性的问题，提出一种改进的高斯金字塔构建方法，该方法从 构建高斯金字塔的原始意义出发，大幅减少了所需的运算时间和存储单元。同时提出并验证了合适的SIFT 参数配置，以及 具体的硬件优化和并行实现方案，使整个系统可以在一片单独的FPGA 芯片上实现。该系统读入串行像素数据流，输出关键 点的特征描述符，并采用256×256 的图像对其进行了仿真验证，结果表明完全达到了实时的效果。 关键词：特征点 实时 尺度不变特征变换 现场可
vhdlmatlabandsimnlinklllllllllkkkk
- 本文件是 基于ＦＰＧＡ的数字电路滤波器设计-This document is based on the number of FPGA circuit filter design
ImageProcessing
- 应用不同的用户可选择回旋滤波器的图像处理部件。一套PC应用程序将图像档案下载到一个FPGA可访问的存储器阵列。处理过的图像显示在连接的VGA显示屏上。 -Users can choose to apply a different room of the image processing filter components. A set of PC applications will be image files downloaded to a FPGA can access the memory
filter_dds_10.29_7.2
- 一个经过处理的FIR filter, verilog HDL实现在FPGA上-One new design of digital FIR filter , which can be implemented in FPGA kit
1
- 纯方位目标跟踪的伪线性卡尔曼滤波器FPGA实现。-The pseudo linear Kalman filter bearings target tracking FPGA.
image-processing
- 图像处理方面，使用Altera公司的stratix系列的FPGA对图像进行高通滤波和高斯滤波-Image processing, Altera Corporation stratix series FPGA high-pass filter and Gaussian filter image
guided_filter
- 剔除了bug完全可编译运行，是分析guider 滤波，设计其他平台如FPGA等算法的很好的参考。-Excluding the bug can be compiled to run fully, is to analyze the guider filter, designed for other platforms such as FPGA algorithms such as a good reference.
gfilter
- MATLAB里的simulink的dspbuilder设计的图像高斯滤波，可直接运行，并可通过matlab转化到quartus中并下载到FPGA运行-MATLAB simulink in the design of the image of dspbuilder Gaussian filter can be run directly, and transformed by matlab to quartus and downloaded to the FPGA run
sobel
- 基于FPGA的sobel滤波。使用vivado 2014.2实现的YUV图像的sobel滤波。-Sobel filter based on FPGA. YUV image Sobel filtering using vivado to achieve the 2014.2.
13_CMOS_OV7725_Gray_Mean_Filter
- 基于FPGA开发的均值滤波程序，效率很高，非常有用(Based on FPGA development of the mean filter program)