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lcd-code
- 比较完整的LCD接口代码，verilog编写，分为6800和8080两种CPU接口，且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program
yavga
- This core is a simple and small VGA controller. * It drives vga monitors with an 800x600 resolution and 72Hz vertical refresh rate (50MHz pixel clock) * It displays chars on the screen (each char is 8x16 pixels) * It has a customizable chars
Tu767sim
- 一个用Verilog HDL编的656标准图像外同步仿真程序-Synchronous simulation program in a 656 series of standard images using Verilog HDL
lcd
- 这是一个用verilog编写的基于spantan3E编写的spi的驱动程序，完全根据时序发送读ID，返回产品ID-A spi driver verilog written based on spantan3E written, based entirely on the timing of sending read ID, return the product ID
verilogyejingxianshi
- 这是Verilog形成的一个液晶显示的东东，希望可以用到，这个也是经过了各位前辈的运行测试并且成功-This stuff is the Verilog to form a liquid crystal display, and hope can be used after you run a test of the predecessors and success
PS2
- PS2键盘实验－识别0-9和A-F 数码管显示值,利用Verilog实现相关的情况。-PS2 keyboard experiment- Identify 0-9 and AF digital tube display values using Verilog related.
JPEG-Encoder
- JPEG 编码器的verilog实现，已经在XILINX SPARTAN6上实现并验证。-The JPEG encoder verilog implementation has been implemented in a Xilinx SPARTAN6 and verify.
vga
- verilog语言编写的VGA图像显示,此模块可以直接使用，可以帮助你很好地掌握VGA的驱动-Verilog language VGA image display, the module can be used directly, can help you have a good grasp of the VGA driver
PBDC
- Verilog is a one of the famous Hardware Descr iptive Languages (HDL). (VHDL is the other one). Verilog langauage syntax very well matches with C language syntax. This is big advantage in learning Verilog. Logic operators, data types, loops are simila
grayscale
- 灰階(gray-scale)圖像處理(60*60 pixel)controller控制各個程式的地址以及開關，input_mem將資料讀進記憶體，grayscale將讀取資料像素的亮度以數值來表示，將24bit的 像素化成四個8bit的值輸出。接著進入sobel，在此將前面的四個值乘上1或-1個別的相加，得出新的四個值，輸入進shiftcase進行threshold的判斷，大於threshold則表現出白色(255)，小於threshold則表現出黑色(0)，最後將結果存入記憶體out_mem。
vga_stripes_top
- VGA彩条显示,分辨率800*600,使用Verilog显示间隔可设置的红绿条纹,使用工具为xlinx ise.-VGA color display with a resolution of 800* 600, the use of red and green stripes Verilog display interval can be set using tools xlinx ise.
7_to_1-LVDS-dispaly-from-FLASH
- 该代码是基于verilog 实现的代码，可以用于对接受1080P的LVDS视频数据并处理后显示到各种规格的LCD屏幕上，且支持从FLASH中读取BMP的图片数据并实时显示到LCS屏幕-The code is based on the code verilog achieve, it can be used for receiving LVDS 1080P video and data processing displayed on a variety of LCD screen, and sup
base2-8fft-verilog
- 一个实现基2 8点傅里叶变换的verilog程序-A multi-point Fourier transform matlab program, you can see the real and imaginary parts of processed data.
TFT_LCD
- 产生逻辑画面的R/G/B/黑/白等画面的完整verilog源码，通过修改宏定义方便修改成支持各种尺寸的LCD驱动，本源码为RGB格式输出接口-Complete verilog source code generation logic screen R/G/B/black/white screen, etc., by modifying the macro definition modified to support a variety of convenient size LCD driver,
VGAdisplay_picture
- verilog控制VGA显示器显示一幅像素为200*200的图片。-verilog control VGA display a 200 x 200 pixel images.
LAB0
- 用verilog代码控制VGA显示屏显示蓝色屏幕。-The verilog code controls the VGA display to display a blue screen.
LAB22
- 应用verilog编程语言控制VGA显示屏显示一幅图片。-Application verilog programming language control VGA display shows a picture.
DWT_verilog-code
- 图像压缩是图像处理中的一个重要课题，在减少图像尺寸以实时传输和存储方面起着非常重要的作用。许多标准推荐使用DWT进行图像压缩。DWT的计算复杂度对基于DWT的图像压缩算法的实时使用提出了重大挑战。在本文中，我们提出了一种改进的提升方案来计算近似和详细的DWT系数。修正的方程使用右移运算符和6位乘法器。计算中的层级减少到一个，从而最小化延迟和增加吞吐量。ViTEX-5 FPGA上实现的设计工作在180 MHz，功耗小于1W的功率。该设计占用了FPGA上不到1的LUT资源。所开发的体系结构适合于FP