Verilog 编写的60进制的计数器，可以用来设计数字钟、频率计等-count_60 for digital clock using Verilog

介绍了简单的数字钟，verilog语言。包括两位时钟数字和两位分钟数字和两位秒钟数字。-It introduced a simple digital clock, verilog language. Including two digital clocks and digital two minutes and two seconds digits.