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canbus(FPGA)
- 基于FPGA的can 总线设计，采用verilog语言编写。在FPGA的开发环境下，新建一个工程，然后将本文件中的各个源代码添加进工程里，即可运行仿真。-FPGA-based bus design can use verilog language. FPGA development environment, a new project, and then the paper all the source code to add the project, Simulation can be run
delay
- 一个可编程延时，只要输入你想的延时周期就可以延时几个周期-a program delay verilog
qam
- ,用VERILOG语言实现16QAM的数字调制的程序，已经在ISE10.1版本中调试通过 -The introduction of cellular technology greatly expanded the efficiency of frequency use of mobile phones. Rather than exclusively allocating a band of frequency to one telephone call in a large geograp
counter
- implementation of a four bit counter in verilog
Display-a-heart-shape-code
- Display a heart shape code点阵显示爱心形的FPGA Verilog 代码-Display a heart shape code
problem-1
- Problem1 of an assignment in a verilog course
problem-2
- Problem2 of an assignment in a verilog course
problem-3
- Problem3 of an assignment in a verilog course
problem-4
- Problem4 of an assignment in a verilog course
problem-5
- Problem5 of an assignment in a verilog course
CAVLE-h264
- 本压缩文件包含了h.264压缩算法中的CAVLE的编解码模块（Verilog和VHDL两个版本），包含有仿真的testbench测试文件，综合后可以直接使用-The compressed file contains the h.264 compression algorithm CAVLE codec module (Verilog and VHDL both versions), including a simulation testbench test file, can be used d