搜索资源列表
i2c.rar
- 这是一个IIC的接口程序，是夏宇闻编的书《verilog 数字系统设计教程》的IIC的源码，很通俗易懂.rar,This is an IIC interface procedures for Xia Wen book " verilog Digital System Design Guide," the source of the IIC, it is easy to understand. Rar
OVL
- OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合、测试平台与验证-OVL- assertion-based verification of Verilog Verilog digital system design: RTL synthesis, test and verification platform
lizi
- 王金明编著的数字系统设计关于另外一种通用硬件描述语言书上的所有例子-Wang Jinming edited the " Digital System Design and Verilog HDL" book on all the examples
cfifo_ptrs_binary
- system verilog fifo env
uart
- i like verilog VHDL and system Verilog
sva_labs_public
- system verilog这是一本关于verilog编程语言的教程,对学习verilog语言有帮助-system verilog
uart_regs
- 异步传送系统，提供了顶层文件。帮助初学者理解Verilog的使用。有很大的教育意义。-Asynchronous transmission system, providing top-level document. Help beginners understand the use of Verilog. Have great educational value.
SC16C752B
- The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission
my38decoder
- 这个是用verilog语言写的一个38译码器的程序，在DE2最小系统板里验证过 -This is to use verilog language is written a and decoder program, in DE2 minimum system board validated
led_decoder
- 这个是用verilog语言写的一个点亮LED灯的程序，在DE2最小系统板里验证过-This is to use verilog language written by a light LED lights program, in DE2 minimum system board validated
VERILOG
- 王金明老师的数字系统设计与Verilog HDL中，讲述的100个实例的Verilog源代码-Wang Jinming teacher " Digital System Design with Verilog HDL" about 100 instances of Verilog source code
Timing
- 此为时域均衡的程序，主要用于OFDM接收系统，用verilog编写，很好-This time domain equalization program, mainly for OFDM receiving system, written in verilog good
CooperativeCommunication
- 1. 研究空时分组码的编译码原理及算法； 2. 研究了几种不同的协作分集系统模型和协作分集协议； 3. 将空时分组码编译码器与协同通信用硬件描述语言Verilog实现，并在ISE集成环境中综合仿真，结果正确后下载到FPGA电路板上； 4. 用示波器观察输出数据是否正确，验证空时分组码协同通信的性能。 -1. Decoding Principles of space-time block codes and algorithms 2. Study several differen
Ch3
- 《Modelsim电子系统分析及仿真》配盘第三章，全部为verilog HDL代码-" Modelsim electronic system analysis and simulation" with the second chapter of the disk, all for verilog HDL code
Ch4
- 《Modelsim电子系统分析及仿真》配盘第四章，全部为verilog HDL代码-" Modelsim electronic system analysis and simulation" with the fourth chapter of the disc, all for verilog HDL code
Ch6
- 《Modelsim电子系统分析及仿真》配盘第六章，全部为verilog HDL代码-" Modelsim electronic system analysis and simulation, with the sixth chapter of the disk, all verilog HDL code
Ch7
- 《Modelsim电子系统分析及仿真》配盘第七章，全部为verilog HDL代码-The Modelsim electronic system analysis and simulation with Chapter VII of the disk, all of Verilog HDL code
Desktop
- system verilog parameter usage
cal_pipeline
- 用system verilog 来实习的 1 stage pipeline calculator. It has been successful compiled in Modelsim-System Verilog Calculator
Verilog第六章
- 数字系统设计与Verilog王金明第四版 第六章课后习题参考解析(Digital system design and the fourth edition of Verilog Wang Jinming The sixth chapter after class exercise reference analysis)