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butfly4
- 基4-FFT蝶形单元实现，按照FPGA内部的乘法器功能编写的-4-FFT butterfly-based unit to achieve, in accordance with the internal FPGA multiplier feature prepared
eda
- 课程设计要求设计并用FPGA实现一个数字频率计,功能：频率计。具有4位显示，能自动根据7位十进制计数的结果，自动选择有效数据的-Curriculum design to design and FPGA implementation of a digital frequency meter, function: frequency meter. With four shows that will automatically count 7 the results of the metric sys
gam6
- FPGA Implementation ofLow Power 64-Point Radix-4 FFT Processor for OFDM System
8.4-ADC0809-
- 基于VHDL语言，实现对ADC0809简单控制,ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟信号，这里由FPGA的系 --统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。 -Based on VHDL ADC0809 simple control, ADC0809 no internal clock, an external clock signal of 10KHz ~ 1290Hz here by the Departm
CooperativeCommunication
- 1. 研究空时分组码的编译码原理及算法； 2. 研究了几种不同的协作分集系统模型和协作分集协议； 3. 将空时分组码编译码器与协同通信用硬件描述语言Verilog实现，并在ISE集成环境中综合仿真，结果正确后下载到FPGA电路板上； 4. 用示波器观察输出数据是否正确，验证空时分组码协同通信的性能。 -1. Decoding Principles of space-time block codes and algorithms 2. Study several differen
BCD_ok-BCD
- Verilog 4位计时器,可以在CPLD开发板上成功运行-Verilog CPLD FPGA
sn74181
- 4位运算器采用sn74181，是采用Verilog hdl编程，是实现fpga的代码，实现了其模块的48种功能，-4 operator uses sn74181, is the use of Verilog hdl programming, is to achieve the fpga code, achieved its module 48 kinds of functions,
encodercount
- 运行在labview实时环境下，FPGA中的ABZ相光电码盘计数器，4细分，可重置-Labview run in real-time environments, FPGA ABZ phase of the photoelectric encoder counter, four segments, can be reset
adder4
- 利用硬件语言FPGA Verilog语言实现4位加法器的运算-Using FPGA hardware language Verilog language implementation and operation of four adder
the-FPGA-taxi-billing-program-
- 出租车计费的硬件设计分为5个模块：1.车轮脉冲计数模块；2.里程计数模块；3.计费模块；4动态扫描模块；5译码模块-The taxi billing hardware design is divided into five modules: 1. The wheels pulse counting module 2. Mileage counting module 3. The billing module 4 dynamic scanning module 5 decoding mod
cc
- nexys 4 fpga board design that must include in program-nexys 4 fpga board design that must include in program....
number_display
- FPGA控制4个7段数码管动态显示，可以为FPGA其他实验做校验中间结果使用- FPGA control 4 LED Segment Displays to dynamic display, can be used for FPGA other experiments to do check the results of the middle