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Useful_data
- Full flow descr iption of the flow of developing the verilog code in ISE and steps in implementing and executing in fpga
UART_RS232(verilog)
- /本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作
mydcm1
- 基于verilog的FPGA里dcm模块分频偏移程序-dcm Frequency offset
Combinational-logic-circuit
- fpga verilog 组合逻辑电路代码仿真及说明-fpga verilog combinational logic circuit simulation code and descr iption
Sequential-logic-circuits
- fpga verilog时序逻辑电路 代码仿真及说明-fpga verilog sequential logic circuit simulation code and descr iption
16QAM-modulation-based-on-FPGA
- 基于FPGA的16QAM调制程序,基于verilog开发环境-16QAM modulation program based on FPGA-based development environment verilog
adder4
- 利用硬件语言FPGA Verilog语言实现4位加法器的运算-Using FPGA hardware language Verilog language implementation and operation of four adder
vftvdr
- 基于FPGA的DDS信号发生器设计，包含Quartus 的工程，打开即可使用，Verilog 语言编写！-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读 显示对应的拉丁字符的拼音 字典- 查看字典详细内容-FPGA design, including the Quartus project, open to use, Ve
fp_prj
- FPGA Verilog 分频程序。用于板子验证及检测功能测试非常方便 -FPGA Verilog program , use for the board analyst and test . very helpfull
OExp13-SOC
- 使用Verilog编程搭建的测试平台，并连接了VGA等外设，使用MIPS汇编编写逻辑完成的躲避球小游戏(Use Verilog programming to build the test platform, and connect the VGA and other peripherals, using MIPS assembly to write logic to complete the dodge ball game)