利用有限状态机实现一般时序逻辑分析的方法； 进掌握用Verilog编写的有限状态机的标准模板-Finite state machine to achieve general sequential logic analysis method into the grasp of finite state machines using Verilog standard template

fpga verilog 组合逻辑电路代码仿真及说明-fpga verilog combinational logic circuit simulation code and descr iption

fpga verilog时序逻辑电路 代码仿真及说明-fpga verilog sequential logic circuit simulation code and descr iption

使用Verilog编程搭建的测试平台，并连接了VGA等外设，使用MIPS汇编编写逻辑完成的躲避球小游戏(Use Verilog programming to build the test platform, and connect the VGA and other peripherals, using MIPS assembly to write logic to complete the dodge ball game)