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counter
- 基于CPLD的计数器 实现光纤测距，包含与单片机的时序控制 Verilog 实现 通过仿真
timeclock
- 数字钟的verilog实现程序。包含各个模块。分别为顶层模块，小时计数器，分计数器，秒计数器等。-Digital clock verilog implementation process. With each module. Were top-level module, hours counter, minutes counter, second counter and so on.
Decade-Counter
- The file contains source code verilog for counting number of 1s
Johnson-counter-with-verilog-design
- the file contains verilog code for johnson counter
Mod13-counter-with-verilog-design
- verilog code for mod13 counter source code-verilog code for mod13 counter source code
ringcounter-with-verilog-design
- Ring counter souce code in verilog