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TheResearchoftherealtimesignalprocessingofSARbased
- 3．完成系统的FPGA程序开发与调试，主要包括FFT，IFFT，CMUL和转置 存储控制等模块，在此基础上，重点介绍了一种基于DDR SDRAM的行写行读高 效转置存储算法，在采用该算法进行转置存储操作时，读写两端的速度相匹配， 满足流水线操作要求，提高了整个系统的实时性。最后介绍了采用CORDIC算法 实现复图像求模运算的方法，分析了算法的硬件实现结构，并给出了基于FPGA 的实现方法及仿真结果。-he FPGA s development and debugging ar
S5PC100_UM_REV1.04
- Samsung s new ARM cpu datasheet. S5PC100 Spec. - CPU ARM Cortex-A8 667-833Mhz - 32KB L1, 256KB L2 Cache - Video 720p (1280x720 Play. h.264 divx, mp4...) - nand, sd/mmc, usb booting - Windows CE 6.0, Linux (*Android) support - support 1
BS2S7VZ7306A
- 这是我设计使用到的机顶盒相关芯片的配套DDR,128M内存，完美设计。-This is my design to set-top box associated with the matching chip DDR, 128M memory, perfect design.
sdram_introduce
- sdram内存技术指南（sdr,ddr,ddr2,ddr3）-sdram memory technology guide (sdr, ddr, ddr2, ddr3)
Datasheets
- Mobile DDR SDRAM MT46H32M16LF – 8 Meg x 16 x 4 banks MT46H16M32LF/LG – 4 Meg x 32 x 4 banks TFT-G240320LTSW-118W-E 16-megabit 2.5-volt or 2.7-volt DataFlash K9F1G08X0A S25FL032P S25FL032P Cover Sheet 32-Mbit CMOS 3.0 Volt Flash Memory
Design-and-implementation-of-High-Speed-Pipelined
- Design and implementation of High Speed Pipelined DDR SDRAM memory Controller
ddr2.pdf
- JEDEC DDR 2 memory interface specification document
ALI_M1621(71)
- M1671 - P4 Super North Bridge – CPU, AGP, PCI and Memory Controller The M1671 is a high-performance, high-value North Bridge that supports all Pentium 4 processors. With internal 128-bit architecture optimized for CPU bus, DDR and AGP4X
DDR
- ddr memory design basics intro