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FPGA-based high-order FIR filter design
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简易fir滤波器，采用分布式算法实现，verilog-Simple fir filter using distributed algorithm, verilog
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FIR filter using verilog code
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b channel FIR filter verilog
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最长的那个句子，求sum的赋值语句就是FIR滤波器的计算过程，将二进制乘法转化为移位运算。对于小数点后的乘数是向左移，小数点前的乘数是往右移位。
-The longest sentence, find the sum of the assignment statement is the calculation of the FIR filter, the binary multiplication into shift operation. Multiplier after the deci
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verilog—FIR滤波器程序，可移植性强，可以借助FDAtool设计滤波器系数，写到本程序里即可-verilog-FIR filter process, portability, and can make use of FDAtool design filter coefficients, the program can be written to
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基于verilog的高通fir数字滤波器设计-Verilog fir digital high-pass filter design based on
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code for FIR filter using verilog hardware descrption language
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