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DJDPLV_LWB
- 利用超高速硬件描述语言(VHDL)在现场可编程逻辑门阵列(FPGA)上编程实现的纯数字式等精度频率计，不但具有较高的测量精度，而且其测量精度不会随着被测信号频率的降低而下降。为了实现对任意信号进行频率测量，在前端输入加整形电路即可。-use ultra-high-speed Hardware Descr iption Language (VHDL) in field programmable logic gate array (FPGA) series The way to achieve su
pinlvji
- 这是一个基于FPGA的频率计和相位计的设计方案-This is an FPGA-based Cymometer and design phase of the program
EP1C3_12_8_GW481
- 等精度频率计 基于fpga的等精度频率计设计 利用Quartus||进行仿真-And other precision frequency meter fpga based design of equal precision frequency meter using Quartus | | simulation
FPGA-based-frequency-counter
- 文章主要介绍了使用VHDL实现数字频率计的功能，其中包含了各部件的VHDL语言描述，仿真和大致硬件框图，对于初学EDA者大有帮助。-The article introduces the VHDL realization of the functionality of the digital frequency meter, which contains the hardware block diagram of the various components of the VHDL languag
digital-frequency
- 此文档详细描述基于FPGA的数字频率计的设计过程-This document describes in detail the design process of FPGA-based digital frequency
FPGApinlvj
- 基于FPGA的频率计程序，是用VHDL语言编写的，通俗易懂。-FPGA-based frequency meter program
fpga
- 这是一个利用verilog HDL语言编写的自动频率计设计项目，能运行-This is a verilog HDL language automatic frequency meter design projects, and be able to run
pilvji
- FPGA关于简易数字频率计的设计方案，其中包括源代码和部分仿真结果-FPGA on simple digital frequency meter design, which includes source code and some simulation results
module-sj001
- 这是基于fpga设计的数字频率计每个模块的 verilog hdl-This is based on verilog hdl fpga design of digital frequency meter for each module
FPGAExampls
- FPGA有价值的27个例子，其中包括LED控制，频率计，电子琴等基于状态机的经典例子，简单的编码调制等等。源代码以文档形式给出。-Examples of valuable FPGA 27 includes an LED control, frequency, keyboard, etc. The classic example of a state machine based on the simple coding and modulation and so on.
jyfpgadszplj
- 基于FPGA的数字频率计设计 具体描述了数字频率计的设计过程及实现步骤-FPGA-based digital frequency meter digital frequency meter is specifically described in the design process and implementation steps
sopc_pinlvji
- 基于FPGA的SOPC高精度频率计，能通过LCD12864显示频率、周期、脉宽。-FPGA-based SOPC precision frequency meter, through LCD12864 display frequency, period, pulse width.
shuzupinlvji_
- 使用FPGA开发，包含数字频率计完整报告，电路图和源码。-Using FPGA development, including digital frequency meter complete report, circuit diagram and source code.
div1_feng
- 用verilog实现除法的功能，其中可以实现整数的除法，并有小数的表示。(verilog divider function ise fpga frequency)
kese0
- 频率计等精度测量测频测周期测相位 运用Verilog语句 在FPGA(asdsssfdfsdffjtfjtjrtrt)
Verilog-数字频率计
- 实现了利用verilog在FPGA系统上实现的数字频率计，三个档位可供选择。(The digital frequency meter implemented on the FPGA system by Verilog is realized, and three files can be selected.)