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FPGA
- 基于 FPGA 的运动目标检测系统的研究与开发 希望有哪位朋友需要-FPGA-based Moving Target Detection System for a friend who would like to have necessary
trafficlight
- 基于quartus 6.0的课设设计，非源码，系统设计方案-Quartus 6.0 based on the design of the class-based, non-source, system design
FPGAdeguangshanjiancejishu
- 本文档设计了1光栅位移传感器信号的接收、光栅位移传感器信号的整形及电平转换电路设计，用Verilog HDL描述了锁相倍频细分和零位信号处理电路。利用FPGA实现光栅位移系统与上位机接口的电路原理框图-This document designed a grating displacement sensor signal reception, grating displacement sensor signal shaping and level conversion circuit design
Verilog_shuzisheji
- 本章的目的是想通过对数字信号处理、计算（Computing）、算法和数据结构、编程语言和 程序、体系结构和硬线逻辑等基本概念的介绍，了解算法与硬线逻辑之间的关系从而引入 利用Verilog HDL 硬件描述语言设计复杂的数字逻辑系统的概念和方法。向读者展示一种 九十年代才真正开始在美国等先进的工业国家逐步推广的数字逻辑系统的设计方法-Purpose of this chapter is to through digital signal processing, computing (
syn_fifo
- 基于systemverilog的异步fifo-fifo of design ，system verilog
Writing-Testbenches--
- 介绍如何使用system verilog搭建testbench。-introduce how to use the system verilog to writing testbench
verilog
- 文档给出了verilog数字系统设计的6个实践项目的详细设计过程，包括设计思路、顶层设计和各个模块设计的源码和详细说明-The document gives 6 verilog digital system design practice project detailed design process, including source code and a detailed descr iption of the design ideas, the top-level design and m
Counter_AD
- Parametrized System Verilog code for a Counter with an increade, decrease switch (AD)
BCD_7Segmentos
- System Verilog code to send BCD values to 7 segments displays
DetectorDeSigno
- System Verilog sign detector module if number its negative, gets a2 compliments drops the value and a flag
Decodificador
- System Verilog decodificator. Enters a value(binary), drops hundreds, tens and units in BCD
Clk_Divider
- System Verilog Clock Divider module done with impementation, contains the implementes modules inside too.
ModportInterface
- Example of how to use Modport in System Verilog.
Verilog-DS18B20
- 这是个基于VERILOG的温度采集系统的源程序文档-This is based on the temperature acquisition system VERILOG source document
System-verilog-Overview
- Verilog overwied. it has writing verilog testbench guidlines
Online-Shopping-System-project-Source-code
- In this homework, you will need to compile and simulate a System Verilog program (constraint_mode_ex.sv) which implements multiple constrained-random test. A more detailed descr iption of the program can be found below:
System-Verilog-Introduction
- system Verilog introduction
夏宇闻verilog数字系统设计综合教程
- 夏宇闻的经典书籍：夏宇闻verilog数字系统设计综合教程(Xia Yuwen classic books: Xia Wen Verilog digital system design tutorial)
system verilog constraint layering
- SystemVerilog Constraint Layering via Reusable Randomization Policy Classes
Verilog-数字频率计
- 实现了利用verilog在FPGA系统上实现的数字频率计，三个档位可供选择。(The digital frequency meter implemented on the FPGA system by Verilog is realized, and three files can be selected.)