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用Verilog和VHDL设计状态机的论文
- 详细介绍了用Verilog和VHDL设计状态机的技术。
DDS
- 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
iic_master
- it is a iic source verilog code with its testcase which can act only as master
synopsis_FSM_coding
- synopsis的有限状态机编码方法的文档。 针对synopsis的综合环境，根据其综合工具的特点说明安全可靠、速度适合的FSM编码风格。 FSM coding style under synopsis. Used for verilog or vhdl designer. Good study data for ASIC newhand.-synopsis of the finite state machine coding documents. Synopsis for the in
VHDLtoVerilog
- VHDL转Verilog的小软件，绝对能用。转换效果还可以-VHDL to Verilog software
UART_DESIGN
- The use of hardware descr iption languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level descr iption not only increases design productivity, but also provides unique advantages for design verif
FPGAFIR
- FPGA-based high-order FIR filter design
watchver
- watchdog with verilog
async_transmitter
- 该程序为RS232串口通信的VERILOG程序，在FPGA上已通过验证，在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0
Verilog
- 是华为的vhdl教程，蛮有用的-Vhdl tutorial is Huawei, quite useless. . . . . . . . . . .
median
- 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1,
NewFolder2
- Verilog and VHDL programs for sipo buffer,d flip flop etc
verilog_hdl_huawei
- 华为verilog，vhdl入门资料。内容浅显易懂，不可多得的好资料。-Huawei verilog, vhdl introductory information. Content easy to understand, rare good information.
Stepper_controller_MAx
- stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog quartus and modelsim implementation is also awailable -stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog qu
verilog
- A popular cookbook describing the Verilog language for the design of integrated circuits. Verilog is the alternative to VHDL and is the favoured HDL design language in the USA. It is easier (quicker) to learn than VHDL because it is not so tightly ty
IIC_slave_core
- iic 总线规范和多个iic Verilog的设计论文,均为pdf-pdf of verilog iic
source_code
- verilog code fifo memory usb
Verilog+lab+3+-+HTN+lab+2
- a lab by vhdl, let discover and enjoy it now
Watch
- Design Watch with set time by Verilog for kit DE2