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phase_test
- 基于verilog的鉴相器设计，鉴相器是锁相环的一部分，功能是检测两个时钟是否同步-The phase detector based on verilog design, PLL phase detector is part of function is to test whether the two clock synchronization
A-Verilog-Model-of-Universal-Sequence-Detector.ra
- a verilog model of universal seq detector
DetectorDeSigno
- System Verilog sign detector module if number its negative, gets a2 compliments drops the value and a flag
renmin331
- FPJA Verilog序列检测器1001 -1001 Sequence Detector