搜索资源列表
-
0下载：
经典计算机体系结构RISC8的源代码（Verilog），包括CPU、内存、寄存器等的实现-classic computer architecture RISC8 the source code (Verilog), including CPU, memory, such as the realization Register
-
-
0下载：
it is a iic source verilog code with its testcase which can act only as master
-
-
0下载：
VGA驱动及显示程序，用Verilog编写代码实现VGA的驱动和显示，并且提供了测试程序Testbench通过测试能得到正确的时序波形。-the source code for driving VGA and displaying the images,the testbench was offered.
-
-
0下载：
verilog source code for uart design
-
-
0下载：
实现乘法功能，用verilog语言可以编译的乘法程序源代码-The realization of multiplication functions, verilog language can be used to compile the source code of the multiplication process
-
-
0下载：
verilog i2c 控制源代码，包括读写控制-verilog i2c source code control
-
-
0下载：
xilinx hdmi tx rx verilog code datasheet
-
-
0下载：
该源代码是用FPGA实现数字锁相环的逻辑，有需要的可以借鉴参考一下。-The source code is to use FPGA implementation of digital phase-locked loop logic, those in need can draw reference.
-
-
1下载：
对DDR控制器的FPGA实现及其代码和参考注释-verilog source code written to read and write DDR
-
-
0下载：
verilog的各种编程实例 有源代码的从简单到复杂-verilog source code of various programming examples from the simple to the complex
-
-
0下载：
串并转换器的verilog源代码带testbench文件-String and converter verilog testbench file with the source code
-
-
0下载：
基于ISE 用verilog编写的uart串口通信源码-Based on the ISE written in verilog uart serial communication source code
-
-
0下载：
文档给出了verilog数字系统设计的6个实践项目的详细设计过程，包括设计思路、顶层设计和各个模块设计的源码和详细说明-The document gives 6 verilog digital system design practice project detailed design process, including source code and a detailed descr iption of the design ideas, the top-level design and m
-
-
0下载：
本书介绍了大量的经典的FPGA开发实例，并附有源代码，是一本很难得外文书籍。-This book presents a classic instance of the FPGA development, together with the source code, it is difficult to get a foreign language books.
-
-
0下载：
这篇文档主要是描述了fifo的作用，里面有用verilog写的源码，及其综合后的结果-This document mainly describes the role of the FIFO inside useful verilog to write source code, and its consolidated results
-
-
0下载：
完成通信系统中数据交织器的设计的设计，要求用Verilog HDL编程，包括源程序，仿真波形和实验结果及分析结论等。
-Completed the design of the communication system data interleaver design requirements using Verilog HDL programming, including source code, simulation waveforms and experimental results an
-
-
0下载：
DDS设计的源代码 用于生成高精度的DDS程序 VERILOG-VERILOG DDS DDS program design source code used to generate high-precision
-
-
0下载：
本程序为捷变频信号的verilog源代码设计实现的仿真，并含有相应捷变频信号在MATLAB仿真的结果-The procedure for the Czech Republic converted signal verilog source code design and implementation of the simulation, and the Czech Republic frequency signal containing the corresponding simulation
-
-
0下载：
In this homework, you will need to compile and simulate a System Verilog program
(constraint_mode_ex.sv) which implements multiple constrained-random test. A more detailed descr iption of the program can be found below:
-
-
0下载：
针对CY7C68013在SLAVE FIFO 模式下读写Verilog源代码-For CY7C68013 in the SLAVE FIFO mode to read and write Verilog source code
-
