搜索资源列表
Verilog_Simulation
- Verilog simulation 如何用verilog写Test bench末进行仿真-Verilog simulation It describe how to write a test bench in veriog for design simulation.
how_to_write_TestBench
- Verilog的testbench写法。网上搜集的内容。有好几个文档。-Verilog for testbench written. Online collection of content. There are several documents.
A-Verilog-HDL-Test-Bench-Primer
- 学习资料：详细说明了如何用Verilog语言编写Testbench文件-Learning materials: detailed descr iption of how to use Verilog language Testbench file
codes
- verilog code for traffic light controller and test bench for verification purpose