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firfpga
- 在利用FPGA实现数字信号处理方面，分布式算法发挥着关键作用，与传统的乘积-积结构相比，具有并行处理的高效性特点。详细研究了基于FPGA、采用分布式算法实现FIR数字滤波器的原理和方法，并通过Xilinx ISE在Modelsim下进行了仿真。 -FPGA using digital signal processing, distributed algorithm plays a key role with the traditional product-plot structure compa
FPGA_of_Median_Filter
- Median Filter 在FPGA中的实现
329
- AN FPGA-BASED IMPLEMENTATION FOR MEDIAN FILTER MEETING THE REAL-TIME REQUIREMENTS OF AUTOMATED VISUAL INSPECTION SYSTEMS
IIRfilterFPGA
- 介绍了IIR 滤波器的FPGA 实现方法,给出了 IIR 数字滤波器的时序控制、延时、补码乘法和累加四个模块的设计方法,并用VHDL和FPGA 器件实现了IIR 数字滤波。-Introduction of the IIR filter FPGA implementation method of IIR digital filter timing control, delay, multiplication and accumulation complement the four modules
Digital Filter implementation by FPGA
- 1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis 2. fpga implemention of a median filter 3. fpga implementation of digital filters 4.hardware acceleration of edge detection algorithm on
firfilter
- Filter designed in fpga
FPGAFIR
- FPGA-based high-order FIR filter design
FPGAfir
- FPGA实现FIR抽取滤波器的设计 采用基于分布式思想的方法来设计FIR滤波器。-FPGA realization of FIR decimation filter design ideas based on a distributed approach to design FIR filters.
jifenlvboqi
- 为了解决软件无线电通信系统中频采样之后的极大数据量在基带处理部分对DSP计算的压力,常采用多速率处理技术.多速率处理过程中需要使用积分梳状滤波器、半带滤波器和高阶FIR滤波器.在分析了积分梳状滤波器的结构和特性的基础上,阐述了多级CIC滤波器一种高效的FPGA实现方法,该方法的正确性和可行性通过Quartus Ⅱ的时序仿真分析得以验证,实际中可以推广应用.-In order to solve software-defined radio communications system after I
median
- 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1,
DesignandFPGAImplementationof
- In most cases, a bandpass filter characteristic is obtained by using a lowpass-to-bandpass frequency transformation on a known lowpass transfer function. This frequency transformation controls the location of passband edges and transfer zero
AReconfigurableFIRFilterSystemBasedonFPGA
- 本文将FPGA的快速性和计算机的灵活性通过USB2．0总线有机地结合起来，设计了一个基于FPGA的可调参数FIR滤波系统。此系统由计算机根据各种滤波器指标计算出滤波参数，通过USB2．0对FPGA芯片内部的FIR多阶滤波器进行参数配置，实现数字滤波器参数可调；配置后的FPGA滤波单元完成对A／D采集的信号进行滤波运算，滤波后的数据经过缓存后通过USB2．0总线传输至计算机进行显示、分析和储存等进一步处理。在系统中采用有限状态机对FPGA参数配置模式和滤波模式进行切换，保证了系统的有序运行。-In
sobel_filter
- implementation of SOBEL filter using FPGA board RC200 in handle-c
FPGA-FIR
- FPGA实现 FIR数字滤波器方案研究！-FPGA implementation of FIR digital filter program.
design-of-cic-filter-based-on-FPGA
- 基于FPGA的CIC滤波器设计，希望对大家有用。-design of cic filter based on FPGA.
FPGA-AFC-Phase-tracking
- 本论文主要研究并设计实现了扩频通信接收系统的跟踪模块，接收系统主要由数字下变频、数字匹配滤波器、差分解调、自动频率跟踪处理等模块组成。-This paper mostly introduces and implementes the receiving system, the receiver unit mainly consisted of the digital down converter, matched filter, differential demodulator, output
zhongzhilvbo
- 中值滤波的ＦＰＧＡ（Verilog语言）实现方法，可以作为通信，图像专业的编程参考， -Median filter FPGA (Verilog language) implementation can be used as communication, professional programming reference image,
FPGA-design-of-wavelet-filter
- 基于Verilog的小波滤波器程序设计的总结文档。-Verilog based wavelet filter program design summary document.
Farrow-filter-error
- 用 Farrow 结构滤波器对并行采样信号进行时间误差校正, 通过 DSPBuilder 软件将设计的滤波器模型转化为硬 件语言, 利于 FPGA 实现-The Farrow filter is used to correct the time error of the parallel sampling signal, and the designed filter model is converted to hard by DSPBuilder software
Design--of-FIR-digital-filter
- 西北工大2006-基于FPGA的FIR数字滤波器的设计和实现-Design and implementation of FIR digital filter based on FPGA in Northwest China