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- Verilog and VHDL programs for sipo buffer,d flip flop etc
Jkflipflop
- it s a vhdl code for jk flip flop in vhdl
Srflipflop
- it s a vhdl code for sr flip flop
cpld_kit_test
- VHDL code to implement basic gates and counter,Flip=Flop,Registers using Xilinx Platform.
SR_Flip_Flop_Program
- SR Flip-Flop Using VHDL
vhdl
- library ieee use ieee.std_logic_1164.all entity decoder is port (clk:in std_logic clr:in std_logic data_in:in std_logic --待解码信元输入端； data_out:out std_logic) --解码信元输出端； end decoder architecture behave of decoder is component dff2
VHDL_trigger
- 本实验是VHDL的触发器实现，将基本RS触发器，同步RS触发器，集成J-K触发器，D触发器同时集成在一个CPLD芯片中模拟其功能，并研究其相互转化的方法。-This experiment is the trigger of VHDL realize, will be basically RS flip-flop, synchronous RS flip-flop, the integrated JK flip-flop, D flip-flops simultaneously integrate