搜索资源列表
Quartus IP核的使用方法和处理方法
- Quartus IP核的使用方法和处理方法，里面介绍的很详细讲的是IP核的的设计方法。-Quartus IP core using the method and approach, which describes in great detail about the IP core design approach.
SOPCVGAIP3090114
- 基于 SOPC 的 VGA IP 核设计-Based on SOPC the VGA IP core design
SOPCVGAIP
- 基于sopc的vga ip核设计参考文档-Based on SOPC vga ip-core design of the reference documentation
08Tutorial3
- tutorial of xilinx ip core
USB_IP
- 介绍了采用FPGA实现USB2.0 IP核的详细方法和步骤以及仿真方法-This paper introduces an FPGA to achieve the USB2.0 IP core in detail the methods and steps as well as the simulation method
de2_sd
- 大学计划里面的sd卡ip核，非常有用。在de2板子上可以非常方便使用-University plans to sd card inside ip core, very useful. In the de2 board can be very easy to use
51_IP_CORE
- 用HDL硬件描述语言写成的MCS51系列单片机IP核，其中包括4位的MCU，内容系4篇硕士论文，其中两个需要用CAJ阅读器打开 -HDL Hardware Descr iption Language with written MCS51 Microcontroller IP core, including 4-bit MCU, the contents of a master' s thesis, Department 4, two of which need to open the
d
- IP核应用，详细的介绍了关于FPGA中IP核的应用-IP core application, a detailed presentation on the application of FPGA in the IP core ,,,,,,
QuartusII-free-of-charge-to-use-IP-Core
- 本文详细的介绍了QuartusII中免费IP核的使用方法-This paper introduces QuartusII free of charge to use IP Core
USB2.0DeviceControllerIPCoreDesignandVerification.
- USB2．0设备控制器IP核的设计与验证-USB2.0 Device Controller IP Core Design and Verification
FPGA_RS232
- 为增加系统稳定性，减小电路板面积，提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性，可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous ser
CPCI_PCIbus
- 为构建一个紧凑、灵活的 CPC I系统,在 IP核的基础上,采用 FPGA来实现 PCI总线接口电路。-To construct a compact and flex ible CPC I syste m, the PCI i nte rface c i rcuit i s i mp l em ented by FPGA based on IP core。
Basic-Multipath-Fading-Channel-Simulator-IP-Core.
- Basic Multipath Fading Channel Simulator IP Core
crc-ip-core-usage
- CRC 编译码IP核的使用方法，仿真图和matlab的结果对比对比，fpga编程时使用-CRC encoding and decoding IP core use simulation in Fig the Matlab results contrast contrast
IP(1)
- 全功能硬件扫描键盘控制器IP核的实现，属于比较前沿的的键盘扫描方法-The realization of the full-featured hardware scanning keyboard controller IP core, belonging to compare the forefront of keyboard scan
IP-Release-Notes-Guide
- 该文件包含xilinx 公司发布的所有IP CORE的介绍，比较全面。-This file contains all the company released xilinx IP CORE presentation, more comprehensive.
FPGA-IP
- FPGA的宏模块介绍，主要是IP核的应用简单介绍-FPGA macro module introduces mainly the application of IP core brief
altera-tse-ip
- MegaWizard_Plug-In工具生成altera三速以太网IP核并编译仿真-MegaWizard_Plug-In tool to generate altera Triple Speed Ethernet IP Core and compile simulation
UART-to-Bus-Core-Specifications
- The UART to Bus IP Core is a simple command parser that can be used to access an internal bus via a UART interface. This core can be used during initial board debugging or as a permanent solution when high speed interfaces are not required. The i
pg137-axi-usb2-device(xilinx USB ip core)
- xilinx USB ip 核使用说明文档，接口完全和usb3320接口一致(Xilinx USB IP core usage instructions document, the interface is completely consistent with the usb3320 interface)