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bai4
- a 16 bits counter using verilog
Mini_Proj3
- Embedded 16 bit adder designed and implemented on Altera FPGA DE1 board using SOPC system builder and tested with NIO2 software. Language:Verilog and C
16bit-Mulitiplier-Verilog-procedure
- 这是一个16位乘法器Verilog程序，包括有符号位和无符号位乘法器-This is a 16-bit multiplier Verilog program, including the sign bit and no sign bit multiplier
16-leading-adder-Verilog-program
- 这是一个16位超前进位加法器的Verilog程序。-This is a 16 bit leading adder verilog program.
ADC_16bit.v
- 一个verilog编写的16位ADC程序。该程序方便了DAC的设计人员对DAC提供输入信号，以此可以获得理想的DAC所需信号-Verilog to write a 16-bit ADC program. The program facilitates the DAC' s designers to provide input signals to the DAC, in order to be able to get a good DAC desired signal
mips.tar
- VERILOG CODE FOR 16- bit ripple carry adder
verilog-code-for-8bit-multiplier-using-vedic-algo
- The vedic multiplier is used perform 16 bit multiplication using urdhva tiryakbhyam sutra. this produces the results with high speed and utilizes low power which is most efficient for the real time processors.
d16to4
- 这是紫外光通信PPM调制设计系统中的16位数据转换为4位数据程序设计。用Verilog语言编辑并且编译成功，希望对大家有帮助-This is 16 PPM modulation design of ultraviolet communication system of the four data programming. Edit and compile successfully with Verilog language, hope to help everyone
csaaa
- csa 16 bit verilog code with less delay
DCC2010-FPGA-CPU16ASM-DCC
- cpu verilog 16 bits to control radio software