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Virtex.files
- 在FPGA系统设计中，要达到性能最大化需要平衡具有混合性能效率的元器件，包括逻辑构造(fabric)、片上存储器、DSP和I/O带宽。在本文中，我将向你解释怎样能在追求更高系统级性能的过程中受益于Xilinx® 的Virtex™ -5 FPGA构建模块，特别是新的ExpressFabric™ 技术。以针对逻辑和算术功能的量化预期性能改进为例，我将探究ExpressFabric架构的主要功能。基于实际客户设计的基准将说明Virtex-5ExpressFabric技术性能平
Advanced-Xilinx-FPGA
- Advanced Xilinx FPGA Design with ISE Objectives Describe Virtex™ -II advanced architectural features and how they can be used to improve performance • Create and integrate cores into your design flow using the CORE Generator™
pBlazIDE36
- There are literally dozens of 8-bit microcontroller architectures and instruction sets.Modern FPGAs can efficiently implement practically any 8-bit microcontroller, and available FPGA soft cores support popular instruction sets such as
DesignandFPGAImplementationof
- In most cases, a bandpass filter characteristic is obtained by using a lowpass-to-bandpass frequency transformation on a known lowpass transfer function. This frequency transformation controls the location of passband edges and transfer zero
GeneratingFPGA-AcceleratedDFTLibraries
- 关于DFT的文章，应用FPGA实现傅立叶变换。-Abstract—We present a domain-specific approach to generate high-performance hardware-software partitioned implementations of the discrete Fourier transform (DFT). The partitioning strategy is a heuristic based on the DFT
DDR2deFPGAsheji
- 使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器以及DDR2 SDRAM操作时序-Using the Virtex-4 FPGA devices to achieve DDR SDRAM and DDR2 SDRAM controller operation timing
Virtex-5-
- 好用的Virtex-5 开发板与套件，基于fpga的嵌入式开发平台-Easy to use Virtex-5 development board with a package based on fpga' s embedded development platform
Using-the-Virtex-Block-SelectRAMP
- The Virtex™ series provides dedicated blocks of on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the block SelectRAM+™ memory can be independently configured as a read/write port, a read port, o
xapp882
- This application note describes the implementation of SERDES Framer Interface Level 5 (SFI-5) [Ref 1] in a Virtex-6 XC6VLX240T FPGA. SFI-5 is a standard defined by the Optical Internetworking Forum (OIF). The interface must operate bidirectionall
GenesysGeneral-ucf
- Genesys™ Virtex-5 FPGA Development Board用户约束文件，来自官方LX50T板子-Genesys™ Virtex-5 FPGA Development Board Genesys--VIP GenesysGeneral-ucf.zip
ddrpspsbf
- 基于FPGA的雷达脉冲预分选器设计--这里, 提出一种基于关联比较器的雷达信 号分选方法,在实现多参数分选的同时, 也保证了实时性。详细阐述了在 Virtex 4 系列 FPGA 上实现基于内容可寻存储器 ( CAM)的关联比较器的途径。-Design of Radar Pulse Signal Pre-sorting Based on FPGA
sha1_v01
- sha1_testbench.v -- Testbench with vectors NIST FIPS 180-2 sha1_exec.v -- Top level sha1 module sha1_round.v -- primitive sha1 round dffhr.v -- generic parameterizable D-flip flop library Performance Analysis Performance equa
eetop.cn_Product_Selection_Guide
- Virtex-6 FPGA Configuration
ADC10D1000_1500RB-Users-Guide-rev1p2
- 高速AD,ADC10D1000,Virtex FPGA,10位，双路1.01.5GSPS，单路2.03.0GSPS ADC。-High speed AD, ADC10D1000, FPGA Virtex, 10 bit, dual path 1.01.5GSPS, single path ADC 2.03.0GSPS.
DSP-with-FPGAs
- Field-programmable gate arrays (FPGAs) are on the verge of revolutionizing digital signal processing in the manner that programmable digital signal processors (PDSPs) did nearly two decades ago. Many front-end digital signal processing (DSP) algo