搜索资源列表
risc8
- 经典计算机体系结构RISC8的源代码（Verilog），包括CPU、内存、寄存器等的实现-classic computer architecture RISC8 the source code (Verilog), including CPU, memory, such as the realization Register
apb.rar
- APB master verilog code,APB master verilog code
Code
- DSP学习板上的例子程序包括 AD转换 CAN总线 SPI SCI -Examples of on-board DSP learning process includes the AD conversion CAN Bus SPI SCI
FPGA_based_infrared_receiver_module
- 基于FPGA的红外接收模块，内含代码，采用VERILOG编写。-FPGA-based infrared receiver module, containing the code prepared by the use of Verilog.
lab3
- verilog source code for uart design
uart
- UART schematic and code
xapp460
- xilinx hdmi tx rx verilog code datasheet
verilog_circuits
- describes the verilog code for logic circuits
median
- 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1,
Stepper_controller_MAx
- stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog quartus and modelsim implementation is also awailable -stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog qu
source_code
- verilog code fifo memory usb
DDRcontroller
- 对DDR控制器的FPGA实现及其代码和参考注释-verilog source code written to read and write DDR
基于FPGA的巴克码发生器与识别器的设计
- 详细介绍了7位巴克码以及帧同步，7位巴克码与帧同步的关系。-Details of the seven Barker code and frame synchronization, 7 Barker code and frame synchronization relationship.
FIR
- FIR filter using verilog code
verilog
- 这是一款学习板的基础实验代码，对于FPGA学习有很好的指导作用。-This is a learning board is based on experimental code, good for the FPGA learning guide。
FPGA--uart(verilog)
- verilog uart 源码，编译器ISE9.1i版本，很有用的源码-verilog uart code
verilog-d-filp-flop
- Verilog code of D-Flip Flop
DAC-TLC5620_
- 基于verilog的硬件设计，DAC芯片TLC5620_verilog代码-The DAC chip TLC5620_verilog code verilog-based hardware design
Georgiou-verilog
- The code added to Figure 4.12.1 to handle bypassing is highlighted
verilog
- 文档给出了verilog数字系统设计的6个实践项目的详细设计过程，包括设计思路、顶层设计和各个模块设计的源码和详细说明-The document gives 6 verilog digital system design practice project detailed design process, including source code and a detailed descr iption of the design ideas, the top-level design and m