搜索资源列表
pll_verilog
- verilog model of a P-verilog model of a PLL
UART_DESIGN
- The use of hardware descr iption languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level descr iption not only increases design productivity, but also provides unique advantages for design verif
FSMFundamentals
- Implementation of a Finite State Machine in Verilog !
Verilog+lab+3+-+HTN+lab+2
- a lab by vhdl, let discover and enjoy it now
Verilog_A
- Verilog-A tutorial for circuit design
Chapter-2-Questions-and-Answers
- this a quiz in verilog programming-this is a quiz in verilog programming
Chapter-5
- this a quiz in verilog programming-this is a quiz in verilog programming
Chapter-10
- this a quiz in verilog programming-this is a quiz in verilog programming
micro-3-quiz-chapter-3
- this a quiz in verilog programming-this is a quiz in verilog programming
DLL-verilog
- verilog model of a D-verilog model of a DLL