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it is a iic source verilog code with its testcase which can act only as master
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VGA驱动及显示程序，用Verilog编写代码实现VGA的驱动和显示，并且提供了测试程序Testbench通过测试能得到正确的时序波形。-the source code for driving VGA and displaying the images,the testbench was offered.
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该源代码是用FPGA实现数字锁相环的逻辑，有需要的可以借鉴参考一下。-The source code is to use FPGA implementation of digital phase-locked loop logic, those in need can draw reference.
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231卷积码的verilog实现，前面是详细的文档说明，有源程序，绝对原创-Verilog achieve 231 convolutional code, preceded by a detailed descr iption of the document, the source, the absolute originality! ! ! !
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完成通信系统中数据交织器的设计的设计，要求用Verilog HDL编程，包括源程序，仿真波形和实验结果及分析结论等。
-Completed the design of the communication system data interleaver design requirements using Verilog HDL programming, including source code, simulation waveforms and experimental results an
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针对CY7C68013在SLAVE FIFO 模式下读写Verilog源代码-For CY7C68013 in the SLAVE FIFO mode to read and write Verilog source code
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