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cy7c68013工作在SLAVE FIFO下的FPGA源代码
- cy7c68013工作在SLAVE FIFO下的FPGA源代码，已经通过，Verilog编写,cy7c68013 slave fifo mode code ,written by hard ware language
iic_master
- it is a iic source verilog code with its testcase which can act only as master
vga
- VGA驱动及显示程序，用Verilog编写代码实现VGA的驱动和显示，并且提供了测试程序Testbench通过测试能得到正确的时序波形。-the source code for driving VGA and displaying the images,the testbench was offered.
RS_decode
- RS编译码算法的实现 RS 码以其强大的纠突发错能力, 被广泛应用于各种差错控制场合。本文讨论了RS 码的编码和译码算 法及其软件实现。-Implementation of RS encoding and decoding algorithm for RS codes with its powerful burst error correcting capabilities, error control is widely used in various occasions. This
verilog_dpll_
- 该源代码是用FPGA实现数字锁相环的逻辑，有需要的可以借鉴参考一下。-The source code is to use FPGA implementation of digital phase-locked loop logic, those in need can draw reference.
juanjima
- 231卷积码的verilog实现，前面是详细的文档说明，有源程序，绝对原创-Verilog achieve 231 convolutional code, preceded by a detailed descr iption of the document, the source, the absolute originality! ! ! !
jiaozhi
- 完成通信系统中数据交织器的设计的设计，要求用Verilog HDL编程，包括源程序，仿真波形和实验结果及分析结论等。 -Completed the design of the communication system data interleaver design requirements using Verilog HDL programming, including source code, simulation waveforms and experimental results an
Verilog_HDLsequence-generator
- Verilog序列产生器，内有代码，可产生随机序列-Verilog sequence generator, which have code that generates random sequences
135--verilog-code-examples
- verilog设计实例，135个简单入门级代码示例-verilog design example, 135 simple entry-level code examples
jishuqi
- 4位二进制的计数器 Verilog 代码-4-bit binary counter Verilog code
14_Lab6
- filter desing using verilog code using matlab
dianzhen
- 点阵图形显示，十字和叉字循环显示，利用verilog语言汇编，有测试代码。-Dot matrix graphic display, cross and cross word cycle display, using Verilog language, assembly, testing code.
QC-LDPC-decoder-FPGA
- 文章提出了一种可以兼容不同码率规则和非规则准循环低密度校验码(LDPC)的部分并行译码结构, 用Verilog语言开发，基于该部分并行结构在Altera公司的StratixII-EP2S90器件上验-This paper presents a part of different bit rates can be compatible with the rules and irregular quasi-cyclic low density parity check code (LDPC) de
rs232_des
- uart verilog code using ram and a-uart verilog code using ram and all
coding-style
- 华为FPGA Verilog代码风格，代码规范，适合新手入门-Huawei FPGA Verilog coding style, standardized code, suitable for beginners
Cy7C68013_SLAVE-FIFO_Verilog
- 针对CY7C68013在SLAVE FIFO 模式下读写Verilog源代码-For CY7C68013 in the SLAVE FIFO mode to read and write Verilog source code