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TheResearchAndIPDesignOfSMBusBasedSmartBattery
- 本文研究了SMBus 规范，介绍了典型的基于片上系统（SoC）设计的知识产权核（IP）实现，采用自顶向下 (Top-down)的集成电路设计方法完成了设计，并架构了基于总线功能模型(BFM)的验证平台 完成功能仿真，顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有 良好的性能。-This paper studies the SMBus specification, based on the introduction of the typical system
design-analyse-protocols
- In the 25+ years the TCP/IP protocol family has been deployed on the internet, it has often faced new problems and challenges. Even today, new extensions such as ECN and TCPs user timeout option, are being added to the core protocols. Newer net
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- IP核应用，详细的介绍了关于FPGA中IP核的应用-IP core application, a detailed presentation on the application of FPGA in the IP core ,,,,,,
The_Linux_Networking_Architecture
- 除了PPP、IP、防火牆、路由、TCP、NAT、UDP及套接字等核心問題外，本書還討論了最新的協議及協議擴展，譬如各種DSL訪問技術中用到的PPPoE協議、Bluetooth(藍牙)四驅動程序及QoS(Quality-of-Service，服務質量)支持等-In addition to PPP, IP, firewall, routing, TCP, NAT, UDP, and sockets and other core issues, this book also discusses the
Basic-Multipath-Fading-Channel-Simulator-IP-Core.
- Basic Multipath Fading Channel Simulator IP Core
out
- A TUTORIAL ON LTE EVOLVED UTRAN (EUTRAN) AND LTE SELF ORGANIZING NETWORKS. The main features of LTE are high peak data rate, flexibility of spectrum usage, low latency times, higher capacity per cell, etc. The radio interface of LTE is based on O
XAUI
- XAUI IP core for 10 GB ethernet or similar
xaui_v10_3
- xaui interface ip core
KSZ8342_Data_Sheet
- IP电话专用芯片 The Micrel KSZ8342Q 文档资料。-The Micrel KSZ8342Q Analog Telephone Adapter (ATA) supplies a complete solution for enterprise and residential environments, converting analog signals from a traditional telephone of fax machine for transmission
Viterbi_Decoder_cn_v6.2
- Xilinx 卷积码译码器IP核v6.2中文翻译，可作为快速入手译码器资料。-Xilinx convolutional code decoder IP core v6.2 Chinese translation, as fast start decoder available.
mt46v16m16_256Mb_DDR
- DDR控制mt46v16m16芯片的指导性文件-ddr IP core control chip mt46v16m16 guidance document
Video Processing Subsystem v2.0 Product Guide
- The Video Processing Subsystem is a collection of video processing IP subcores, bundled together in hardware and software, abstracting the video processing pipe. It provides the end-user with an out of the box ready to use video processing core,