搜索资源列表
SPI-in-Verilog-implementation
- SPI的Verilog实现(非常的全面和详细，还带有SPI算法的注解).-SPI in Verilog implementation (a very full and detailed, but also with the SPI algorithm annotation).
UART_spec
- a UART model with FIFO buffer, design with verilog
iic_master
- it is a iic source verilog code with its testcase which can act only as master
chapter9
- 一个别人写的ＵＡＲＴ ｖｅｒｉｌｏｇ程序，希望对大家有帮助-A UART verilog program written by someone else, we want to help
verilog_example
- verilog实例，多路器，除法器，数字跑表的多种实现方法-verilog example, the multiplexer, a divider, a digital stopwatch many implementations
juanjima
- 231卷积码的verilog实现，前面是详细的文档说明，有源程序，绝对原创-Verilog achieve 231 convolutional code, preceded by a detailed descr iption of the document, the source, the absolute originality! ! ! !
Verilog-HDL
- verilog HDL程序入门，很好学，基本和C语言一样，几天就可以简单的编程-verilog HDL program entry, very good school, Basic and C language, a few days can be a simple programming
Verilog_HDL_basics_online_CN
- 是一本比较精炼但是很全面的Verilog语言教程-Is a more refined but very comprehensive Verilog language tutorial
yinjianmiaoshuyuyanVerilog(disiban)
- 这是硬件描述语言verilog的第四版，希望对大家的学习有帮助。-This is a hardware descr iption language Verilog fourth edition, I hope to learn from everyone.
An-Introduction-to-Verilog---Part-1
- introduction to verilog A
latch
- Abstract—Power is becoming a precious resource in modern VLSI design, even more so than area. This paper proposes a novel architecture for modular, scalable &reusable hybrid constant co-efficient multiplier (KCM) circuit. Comparison is made b
QC-LDPC-decoder-FPGA
- 文章提出了一种可以兼容不同码率规则和非规则准循环低密度校验码(LDPC)的部分并行译码结构, 用Verilog语言开发，基于该部分并行结构在Altera公司的StratixII-EP2S90器件上验-This paper presents a part of different bit rates can be compatible with the rules and irregular quasi-cyclic low density parity check code (LDPC) de
rs232_des
- uart verilog code using ram and a-uart verilog code using ram and all
CAM2006
- Verilog allows you to design your digital design at various abstraction levels.Suppose you have an algorithm to be implemented in the form of a digital circuit then you can easily use Verilog constructs to do the same without worrying about the unde
FpgaFskDemod
- 程序实现一种FSK的解调，语言为verilog。(Program to achieve a FSK demodulation, the language is verilog.)