搜索资源列表
fir-vhdl
- 用Vhdl硬件描述语言编写的FIR数字滤波器-Vhdl using Hardware Descr iption Languages in preparing the FIR digital filter
数字信号处理的fpga实现
- 数字信号处理的fpga实现，用VHDL语言编程实现IIR滤波器,Digital signal processing to achieve the FPGA, using VHDL language programming to achieve IIR filter
-VHDL
- 本报告分两部分： 1 由matlab计算FIR数字滤波器的滤波系数； 2 用VHDL语言设计逻辑电路，再通过QUARTUS II 软件，将各个模块的电路封装成期间，在顶层设计中通过连线，完成整个系统。 -FIR digital filters based on VHDL
FIR
- FIR结构数字滤波器，64阶。在Altera FPGA上验证通过-FIR digital filter structure, 64 bands. Verified by the Altera FPGA on the
FIR-filter-VHDL-code
- 基于FPGA的17阶FIR滤波器VHDL代码。文件附带了FIR数字滤波器理论的介绍。-FPGA-based 17-order FIR filter VHDL code. File with the FIR digital filter theory introduction.
IIRfilterFPGA
- 介绍了IIR 滤波器的FPGA 实现方法,给出了 IIR 数字滤波器的时序控制、延时、补码乘法和累加四个模块的设计方法,并用VHDL和FPGA 器件实现了IIR 数字滤波。-Introduction of the IIR filter FPGA implementation method of IIR digital filter timing control, delay, multiplication and accumulation complement the four modules
Digitalfilter
- 一篇基于FPGA的数字滤波器的小论文，附带有VHDL源码-An FPGA-based digital filter small papers, comes with VHDL source code
data
- fpga嵌入式应用之数字滤波器 里面有部分matlab+vhdl-FPGA embedded applications of digital filters there are some matlab+ vhdl
digital_filter
- 数字滤波器VHDL源码，在matlab下仿真-Digital filter VHDL source code, under the simulation in matlab
VerilogHDL
- 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure an
FIR5
- 5阶数字滤波器FIR5，包括了Textio模拟等完整设计，VHDL-5_level digital filler, including Textio simulation
VHDL_FPGA_FILTER
- 用VHDL语言设计基于FPGA器件的高采样率FIR滤波器,基于VHDL与CPLD器件的FIR数字滤波器的设计-Design using VHDL language FPGA devices based on high sampling rate FIR filter, based on VHDL and CPLD devices, the design of FIR digital filter
17jie_fir
- 采用VHDL语言实现17阶的数字低通滤波器的设计-VHDL language used to achieve 17 the number of bands of low-pass filter design
4
- 基于FPGA的FIR数字滤波器的设计与实现,基于FPGA的FIR数字滤波器的设计与实现-FPGA-based FIR digital filter design and implementation of FPGA-Based FIR Digital Filter Design and Implementation
3
- FIR数字滤波器的优化与验证 -FIR digital filter optimization and verification FIR digital filter optimization and verification
filter
- FIR数字滤波器的实现，采用Kaiser窗实现高精度的地痛滤波器。-The realization of FIR digital filter using Kaiser window filter to achieve high accuracy in pain.
LAB31
- EDA基础_综合实验篇__实验三十一 FIR数字滤波器设计-The basis of comprehensive experimental articles EDA __ _ experimental FIR digital filter design 31
IIR(vhdl)
- 基于fpga的数字滤波器设计的vhdl源代码-Fpga digital filter design based on the vhdl source code
32jie-vhdl-fir
- 32阶数字滤波器 没有时间来得及精简 不好意思了的说 呵呵 -32-order digital filter is not time enough time to streamline embarrassed to say Oh
FIRFILTER
- 16阶数字滤波器 VHDL语言编写 已经全部编译成功-16-order digital filter VHDL language have all been compiled successfully