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32bit.zip
- multiplier and divider verilog codes,multiplier and divider verilog codes
mult
- 32位浮点乘法器的源代码，用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
32-bit_multiplier_model
- 此程序为32-bit乘法器，另附有VHDL测试程序-This procedure for 32-bit multiplier, followed VHDL test procedures
32bit_multiplexer
- 32位高性能浮点乘法器芯片设计研究.pdf-32-bit high-performance floating-point multiplier chip design research. Pdf
FinalFPMultiplier
- Simple 32 bit Floating point Multiplier
harshit1
- 32 bit scalable multiplier architecture
modi3
- sub nano second 32 bit multiplier
chengfaqi
- 乘法器,实现了乘法和除法的功能,能够进行32位的运算-Multiplier to achieve the functions of multiplication and division to carry out 32-bit computing
32bitBoothmultiplier
- 32位布思乘法器VHDL实现，2个32位数相乘-32-bit Booth multiplier VHDL implementation, two 32-digit multiplication
post_norm_mul
- 符合IEEE754标准的32位浮点流水线乘法器 采用移位相加算法，-32-bit floating point pipeline multiplier on IEEE754 standard
ADSP-21262
- High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture— two 32-bit IEEE floating-point
ADSP_2126x_HRM
- High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture— two 32-bit IEEE floating-point
booth_mult
- VHDL code for Booth multiplier for 32bit input
cordic_mpy_100722
- 6bit & 32 bit pipeline CORDIC 乘法器-6bit & 32 bit pipeline CORDIC Multiplier
fpmul
- floatinfg point multiplier 32 bit parellel processing
mul32
- 32位无符号乘法器 采用VHDL语言编写，很容易改为有符号32位乘法器-32-bit unsigned multiplier using VHDL language, it is easy to signed 32-bit multiplier
PARALLEL-MULTIPLIER
- vhdl code for a 32 bit parallel multiplier
wu1_selfcheck_beh_0
- 32位的乘法器，能在ISE软件中进行仿真。能看到仿真效果。-32-bit multiplier, the ISE software simulation. Can see the simulation results.
Vhdl-Implementation-of--Fast-32x32-Multiplier-Bas
- The Vedic mathematics is quite different from conventional method of multiplication like adder and shifter. This mathematics is mainly based on sixteen principles. The multiplier (referred henceforth as Vedic multiplier) architecture base
mul-32
- a pipelined 32-bit 2’s complement array multiplier that utilizes the modified Baugh-Wooley 2’s complement multiplication