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驱动led显示
- //串行驱动led显示， //一个74hc595位移寄存器驱动三极管驱动led位， //两个74hc595驱动led段，方式位5位x8段x2=10个数码管 //5分频，每次扫描时间位1.25ms //定义特殊符号-/ / Serial Driver led, / / a 74hc595 displacement register drives the triode-led drive, / / 2 74hc595 led drive, five-way x8 of x2 = 10 digital
digitalsystemDesign
- 第7章数字系统设计实例 7.1 半整数分频器的设计 7.2 音乐发生器 7.3 2FSK/2PSK信号产生器 7.4 实用多功能电子表 7.5 交通灯控制器 7.6 数字频率计-Chapter 7 Digital System Design Example 7.1-integer dividers designed Music Generator 7.2 7.3 2F SK/2PSK Signal Generator 7.4 Table practical multi-f
led_5
- //串行驱动led显示， //一个74hc595位移寄存器驱动三极管驱动led位， //两个74hc595驱动led段，方式位5位x8段x2=10个数码管 //5分频，每次扫描时间位1.25ms-/ / Serial Driver led, / / a 74 hc595 displacement Driver Register triode-led drive, / / 2 74 hc595 led drive, 5-way x8 of x2 = 10 digital control
Digital_system_design_example
- 数字系统设计实例.pdf,VHDL语言实现，7.1 半整数分频器的设计7.2 音乐发生器7.3 2FSK/2PSK信号产生器7.4 实用多功能电子表7.5 交通灯控制器 7.6 数字频率计.值得一看。-digital system design examples. Pdf, VHDL, 7.1-integer divider design Music Generator 7.2 7.3 2FSK/2PSK Signal Generator 7.4 Practical multi-functi
ClkDiv_2p5
- 2.5分频器。算是小数分频的一个例子。我们以前做实验的时候用来写实验报告滴~还有好多呢，慢慢上传吧~
fen
- verilog，4、5分频器，5分频器占空比3：2-Verilog, 4,5 dividers, five dividers ratio of 3:2
半整数分频器的实现（verilog）
- 半整数分频器的实现（verilog），本文以6.5分频为例！很实用的！,fen pin qi
div5
- 利用VHDL语言描述的5分频器（改变程序中m1,m2值，可作为任意奇数分频器）-The use of VHDL language is described in 5 prescaler (change procedure m1, m2 value, can be used as arbitrary odd prescaler)
freqdiv5
- verilog hdl 实现5分频器设计。
N_Separate-frequency-device
- 可以输入0到2的5次方的任意分频的分频器-Separate frequency device
PFD50
- 分频器，利用D触发器做的2、3、5分频器-Divider, made use of D flip-flop divider 2,3,5
deccount2.5
- 2.5分频器设计,用VHDL编写-2.5 divider design using VHDL
verilog
- Verilog学习例程：4位二进制数的乘法器、5分频器、8位数据寄存器、8位移位寄存器、边沿D触发起门级设计、边沿D触发器行为级设计、同步计数器、异步计数器-Verilog learning routines: 4-bit binary number multiplier, 5 dividers, 8-bit data registers, 8-bit shift register, edge-triggered D gate-level design, level design edge D
code
- 5分频器的源代码编写过程中建议大家先画图，在用代码描写，清楚明了-5divider code， and easy to understand,you will find it is easy to write
Div_Fre
- 5分频器，功能是对需要信号进行五分频，生成周期为原来五倍的信号-5 divider, the fifth of the frequency on the need to signal the build cycle for the original five times the signal
2.5fenpin
- 利用VHDL语言描述的5分频器（改变程序中m1,m2值，可作为任意奇数分频器-The use of VHDL language is described in 5 prescaler (change procedure m1, m2 value, can be used as arbitrary odd prescaler
5.7
- 基于proteus，脉冲分频器，proteus，脉冲分频器-Based on proteus, pulse divider, proteus, pulse divider
4.5fenpingqi
- 基于FPGA的关于verilog语言的4.5分频器及其仿真波形图-FPGA based on verilog language frequency divider and its simulation waveform in figure 4.5
fenpin
- 可以实现n+0.5倍的分频，本程序是利用50MHz的FPGA开发板实现分别实现10MHz，2.5MHz的分频时钟。(N+0.5 times can be achieved frequency division, this procedure is to use 50MHz FPGA development board to achieve, respectively, 10MHz, 2.5MHz frequency division clock.)
新建 WinRAR 压缩文件
- 将一个1Mhz的信号分频成100khz、10khz、1khz、100hz。实验要求每相差十倍频率就有脉冲输出，推荐采用十进制计数器对信号进行分频，即判断输入信号上升沿或下降沿的个数，每计满5个即让输出信号电平翻转，以此实现10分频。(Divide a 1Mhz signal into 100kHz, 10kHz, 1kHz and 100Hz. The experiment requires that every ten times the frequency of the difference