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ismsde2000.zip
- 这是一个把bmp 图像转换成dcm图像的专用程序,This is a bmp to dcm program
dcm.zip
- 该代码可以将dicom图像转为bmp图像，非常方便实用，代码简介明了，易于上手,The code can be dicom image to bmp image, very convenient and practical, brief and clear code, easy to fly
Dcm2bmp-bmp2dcm.rar
- dcm to bmp and bmp to dcm,It is the code that dcm to bmp and bmp to dcm.
DCM
- ISE实现DCM组建例化，得到3倍频时钟-ISE to achieve established cases of DCM, received 3 octave clock
NS-Flyback-DCM
- MathCAD file for the design of Discontinuous Conduction Mode (DCM) Flyback Converter
dcm_test2
- xilinx fpga 倍频的例子，包含整个工程， 如果去用ISE 实现倍频，dcm 用法-xilinx s FPGA dcm example
DCM
- Xilinx公司诸多型号开发版中的一个模块，能够实现1到16次倍频和分频等功能。使用时现在ISE集成开发环境下利用VHDL进行例化。本文档为个人学习总结-Xilinx, a number of models developed version of a module, be able to achieve 1-16 times multiplier and divider functions. ISE now use integrated development environment for
DCM
- xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
dcm2
- 基于Xilinx Vertex4的可综合的二级DCM模块源代码，可生成400Mhz时钟信号-Based on Xilinx Vertex4 of two integrated DCM module source code, can generate 400Mhz clock signal
BUFG_CLK2X_FB_SUBM
- xilinx DCM 应用的源代码，完全可用-xilinx DCM application source code, fully available
BUFG_CLK0_FB_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
BUFG_CLK0_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
BUFG_CLK2X_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
BUFG_CLKDV_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
xapp462_vhdl
- a example -Code for DCM in language VHDL-a example-Code for DCM in language VHDL
plantmodel
- MOdel to control dcM
wtut_sc
- DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock
iii
- DCM图像像素分析DCM图像像素DCM图像像素分析分析-DCM image pixel analysis of DCM-pixel image analysis of the image pixel analysis of DCM
DICOM3
- 1.修改DICOM传输底层服务名。 2.删除FindSCUIsRun属性。 3.删除MoveSCUIsRun属性。 4.删除StopMoveSCU属性。 5.删除StopFindSCU属性。 6.删除OnMoveSCUReceiveFile(sReceivedFileName: String)事件。 7.增加是否将StoreSCP接收文件保存到子目录功能。（StoreSCPSaveFileInSubDir[True=保存到子目录(.\ Modality \ StudyDa