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leon3-altera-ep2s60-ddr
- The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor in
DDR内存接口VC源程序IP核
- 很难看到的 DDR内存接口VC源程序IP核 ！ 各大公司用它卖钱的哦！
DDR-SDRAM_IP_core
- DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
DDR_Xilinx
- xilinx公司DDR控制ipxilinx公司DDR控制ip-xilinx公司DDR控制ip
DDR
- HYB25025616的IP核，可直接用于microblaze的应用里，在合众达FEM024板子直接使用-HYB25025616 the IP core, can be used directly microblaze application, the board in the Triangle over FEM024 directly
DDR_SDRAM_design_and_conclusion
- DDR SDRAM总结文档，描述了DDR IP的设计挑战，接口时序，模块设计原则，调试技巧及应用指南-DDR SDRAM summary document describing the design challenge of DDR IP, interface timing, modular design principles, debugging skills and Application Guide
ddr_ddr2_sdram-ip
- 该程序为Altera 公司 DDR DDR2 SDRAM 的IP源程序安装包，非常有价值的东西，借此网址共享下。-The program for Altera Corporation DDR DDR2 SDRAM of IP source installation package, a very valuable thing, whereby the URL Sharing.
ddr
- ddr2控制器设计,适用于xilinx fpga,内含IP软核 -ddr2 controller design for xilinx fpga, embedded IP soft core
mt46v16m16_256Mb_DDR
- DDR控制mt46v16m16芯片的指导性文件-ddr IP core control chip mt46v16m16 guidance document
ddr_controller
- 完整的DDR控制器设计，包含代码、仿真环境、FPGA综合网表等-full DDR controller ip,include rtl code,simulation environment and testbench, fpga synthesis netlist,etc.
hasannorm
- describe synopsis ommonly use double data rate (DDR) memory IP to boost memory bandwidth, but they often struggle to meet timing budgets for these high-speed interfaces. Designers who incorporate DDR IP into systems-on-chip (SoCs) and use externa
AXI-HP-ZYNQ
- 用Vivado IPI搭建的Zynq-7000 PS到PL通信过程，使用了AXI-HP接口，利用AXI-DMA IP实现直接读写DDR的过程，软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can
xst_vlog_bl2cl25
- DDR 原厂IP核开源代码控制器vrilogHDL代码(xilinx ddr control xst)