搜索资源列表
mlite.tar
- Plasma IP Core 你可以利用这个组件在fpga中设计mips结构的CPU -Plasma IP Core You can use this component in fpga design the structure of mips CPU
MIT_mips_Core.tar
- 麻省理工的一个实验室实现的mips IP CORE，可以在fpga上跑通 -a Massachusetts Institute of Technology laboratory achieved mips IP CORE, the fpga can run on Link
CTDSP
- 本源码经过上机调试,是CT算法在TI的CCS下编程 可以在DSP硬件和软件仿真条件下运行,同时对CT算法在ARM,mips,PC,fpga等上实现都有借鉴意义.搞CT等重建算法的人值得一看
fpga_design_of_a_pipelined_CPU
- 基于fpga流水线CPU控制器的设计与实现：在fpga上设计并实现了一种具有mips风格的CPU硬布线控制器。-fpga design of a pipelined CPU：a hard-wiring CPU controller with a mips-style is designed in fpga.
CU
- mips指令控制器。fpga上板验证实现。为cpu课设重要模块-mips instruction controller.
fpga based-system-design
- 基于fpga系统设计 本案例利用ALTIUM设计一个数字可控的混响系统，在这个系统中将把mips处理器、 IIS 控制器、SPI控制器、SRAM控制嵌入到fpga内部实现图1的功能结构。 -fpga-based system design This case the use of the ALTIUM design a digital controlled reverberation system, mips processors will be in this
mips-processor-Verilog-code
- 原创，mips处理器Verilog源码，在fpga实现单周期mips处理器，实现存储访问指令load word(lw)和store word(sw)，算术逻辑指令add、addi、sub、and、or和slt跳转指令branch equal(beq)和jump(j)-Original, achieves single-cycle mips processor mips processor Verilog source code, the fpga, storage access instruct
Robust and Optimal Control by Kemin Zhou
- Embeded-SCM Develop ARM-PowerPC-ColdFire-mips Embeded Linux SCM VxWorks uCOS DSP program Windows CE VHDL-fpga-Verilog Other Embeded program
s_mips
- fpga verilog mips processor - pipeline reference
VHDLshipincaijixitong
- 利用ALTIUM DESIGNER设计一个CMOS摄像头采集系统，在这个系统中将把mips处理器、IIC控制器、AD视频接口、LCD控制器、SRAM控制嵌入到fpga内部实现图 1的功能结构。-Use of the ALTIUM DESIGNER designed a CMOS camera acquisition system, the mips processor, IIC controllers, the AD video interface, LCD controller, SRAM
VHDLyinpincaijixitong
- 例利用ALTIUM设计一个数字可控的混响系统，在这个系统中将把mips处理器、IIS控制器、SPI控制器、SRAM控制嵌入到fpga内部实现图1的功能结构。 -Patients using the ALTIUM design a digital reverberation system, the system controllable mips processor, IIS controller, SPI controller, SRAM control will be embedded int
fpga_pc_software
- 计算机组成原理课程实验使用软件，Thinpad教学机教学实验软件 实现mips代码到机器代码之间的转换 实现本机和fpga板的通信，将机器代码送入 可在本机编写代码送入fpga板的sram中，fpga板的cpu会运行-Computer architecture course experiment using software, Thinpad teaching machine teaching experiment software mips code into machine co
cpu_design
- fpga mips架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-fpga mips CPU, simple five-stage pipeline function, developed by ISE, using verilog language
minimips_latest.tar
- minimalistic mips core. you can load it to any fpga.
openocd-0.8.0
- OpenOCD provides on-chip programming and debugging support with a layered architecture of JTAG interface and TAP support including: - (X)SVF playback to faciliate automated boundary scan and fpga/CPLD programming - debug target support (
project_1
- 使用fpga实现mips处理器代码verilog-Use Code verilog fpga realize mips processor
mipsx2
- 基于fpga的SOC设计与功能测试，利用mips指令集编写的soc片上系统，以及功能验证- SOC design and fpga-based functional test, use mips instruction set written soc system on a chip, and functional verification
Implement-a-CPU
- 在fpga赛灵思基础3上使用Verilog HDL实现支持mips操作子集的CPU-Implement a CPU which supports a subset of mips operations using Verilog HDL on fpga Xilinx Basys 3
f32c-master
- fpgarduino源码，f32c：VHDL的mips和RISC-V指令集实现(fpgarduino source code, f32c:VHDL mips and RISC-V instruction set implementation)
OExp13-SOC
- 使用Verilog编程搭建的测试平台，并连接了VGA等外设，使用mips汇编编写逻辑完成的躲避球小游戏(Use Verilog programming to build the test platform, and connect the VGA and other peripherals, using mips assembly to write logic to complete the dodge ball game)