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verilog实现的数字频率计8位数码管输出显示同时矩形波分档输出-verilog implementation of digital frequency meter
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verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,
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verilog写的数字频率计的控制模块,对程序进行控制-written in Verilog digital frequency meter control module, the program control
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verilog写的数字频率计的选择模块,用与显示的选择-written in Verilog digital frequency meter option module, used and display options
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Verilog HDL下的4 位数字频率计控制模块源代码-Verilog HDL under four digital frequency meter control module source code
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利用verilog语言，从上至下层次管理的设计思想；Verilog HDL的行为描述和结构描述,实现8位频率计，4个0检测修正电路的原理说明-The use of Verilog language, top-down hierarchical management design idea Verilog HDL descr iption of the behavior and structure of a descr iption of the realization of frequency
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用Verilog HDL / VHDL实现的数字频率计（完整实验报告）-Using Verilog HDL/VHDL realization of digital frequency meter (complete test report)
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a simple implementation of a frequency meter with
the BCD-counter and the 7-segment LED display
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等精度频率计设计与文档，有源码，doc格式-Precision frequency meter, etc. The design and documentation, has source code, doc format
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数字频率计的源码
最大测量频率达到30MHz-Digital frequency meter measuring frequency of the source code to achieve the maximum 30MHz
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Frequency meter Verilog implementation for Xilinx XC2C256. MT10T7 7-seg LCD used for output.
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等精度数字频率计的Verilog源码，从上到下的设计思路，分为6个模块。上过Altera公司的FPGA板。
供大家参考，希望大家不要照抄！-Such as precision digital frequency meter Verilog source code, from top to bottom of design ideas, divided into six modules. Been to Altera' s FPGA boards. For your reference, h
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数字频率计的Verilog HDL语言实现，已经通过仿真-Digital frequency meter Verilog HDL language implementation has been through simulation
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数字频率计
采用Verilog语言编写，分为8个模块，分别是计数器，门控，分频，寄存器，多路选择，动态位选择，BCD译码模块-Digital frequency meter using Verilog language, divided into eight modules, namely, the counter, gated, frequency, register, multiplexer, Dynamic Choice, BCD decoding module
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本项目基于等精度测量频率的原理,利用Verilog硬件描述语言设计实现了频率计内部功能模块,对传统的等精度测量方法进行了改进,增加了测量脉冲宽度的功能 采用STC89C52单片机进行数据运算处理,利用液晶显示器对测量的频率、占空比进行实时显示。充分发挥FPGA(现场可编程门阵列)的高速数据采集能力和单片机的高效计算与控制能力,使两者有机地结合起来。-The project is based on the principle of equal precision frequency measure
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数字频率计FPGA代码，用verilog语言实现。-Digital frequency meter FPGA code with verilog language.
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基于Verilog HDL语言，编写的频率计。-Based on Verilog HDL language, written in frequency meter.
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基于Verilog HDL数字频率计的设计与实现(Design of Verilog HDL Digital Frequency Meter)
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用于FPGA开发，使用VERILOG语言编写，并在QUARTUS II仿真平台仿真，实现频率计的功能。(It is used in FPGA development, written in VERILOG language, and simulated on the QUARTUS II simulation platform to realize the function of the frequency meter.)
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实现了利用verilog在FPGA系统上实现的数字频率计，三个档位可供选择。(The digital frequency meter implemented on the FPGA system by Verilog is realized, and three files can be selected.)
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