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hdl优化设计十大戒律
- hdl优化设计十大戒律-转载-HDL design optimization Ten commandments-reproduced
使用verilog hdl实现16位的cpu设计
- 实现16位的cpu设计 内容使用verilog hdl实现,具体的实现步骤方法,都已经写到文档里面去了!,To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the document went to!
pwm
- pwm的占空比和死区时间可调的Verilog HDL程序设计和测试-duty cycle of pwm and adjustable dead time of the Verilog HDL design and testing procedures
Verilog-HDL
- 《Verilog-HDL实践与应用系统设计》一书中的光盘源文件- Verilog-HDL practice and application of system design, a book on CD-ROM source file
HuaweiFPGAdesignflowguide
- 华为内部的FPGA设计培训教程,详细阐述了设计流程图、Verilog HDL设计、逻辑仿真、逻辑综合。对大家的学习一定有帮助的。-Huawei within the FPGA design training tutorial, a detailed flow chart of the design, Verilog HDL design, logic simulation, logic synthesis. Study of the U.S. must have help.
Verilog_HDL_progamming
- Verilog-HDL程序设计实用教程收集,内容丰富,设计技巧多样。-Verilog-HDL Design Tutorial practical collection, rich in content and variety of design skills.
miaobiao
- 用Verilog HDL编写的秒表设计,可以实现百分之一秒,十分之一秒,秒,十秒等功能。-Verilog HDL prepared with a stopwatch designed to achieve the hundredth of a second, one-tenth of seconds, seconds, 10 seconds and other functions.
Verilog-HDL
- Verilog-HDL实践与应用系统设计-Verilog-HDL Practice and Application System Design
VerilogHDL
- Verilog HDL设计要点在前面学习的基上, 通过本章十个阶段的练习,能逐步掌握Verilog HDL 设计的要点。可以先理解样板模块中每一条语句的作用,然后对样板模块进行综合前和综合后仿真,再独立完成每一阶段规定的练习。-Verilog HDL design points in the previous study based on ten stages of practice by this chapter, can gradually grasp the main points of
verilog
- 第1章 EDA设计与Verilog HDL语言概述 第2章 Verilog HDL基础与开发平台操作指南 第3章 Verilog HDL程序结构 第4章 VERILOG HDL语言基本要素 第5章 面向综合的行为描述语句 第6章 面向验证和仿真的行为描述语句 第7章 系统任务和编译预处理语句 第8章 VERILOG HDL可综合设计的难点解析 第9章 高级逻辑设计思想与代码风格 第10章 可综合状态机开发实例 第11章 常用逻辑的VERILOG HDL实现
design-of-CAN-based-on-VHDL
- 基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计,实现其功能,并且能够在FPGA开发平台Quartos上通过仿真验证,证明其正确性-Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the C
Verilog-HDL--design-skill
- 该文档很好的介绍了verilog的设计方法,讲的比较详细,希望对读者有帮助-A good introduction to the document verilog design methodology, speaking in more detail, hope to help readers
Verilog-HDL-design
- verilog方法逻辑设计教程,教会复杂电路设计的基本-verilog tutorial method of logic design, circuit design of the basic church complex
Verilog-HDL-Design
- FPGA入门的,云创工作室很好地一本书,主要以XILINX公司的芯片为主!-A very good book from Yunchuang studio for FPGA newer,and this book mainly talks about the verilog HDL and the XILINX FPGA!
ch06-3_Verilog-HDL
- Verilog HDL基础Verilog HDL设计模块的基本结构 Verilog HDL的语言规则用Verilog HDL实现各种类型电路及系统设计的方法-The basis of Verilog HDL Verilog HDL design module, the basic structure of the Verilog HDL language rules to various types of circuit and system design using Verilog HDL
Advanced-Digital-Design-with-the-Verilog-HDL-CODE.
- 《Verilog HDL高级数字系统设计》(Michael D. Ciletti著) Verilog HDL源代码-" Verilog HDL Advanced Digital System Design" (Michael D. Ciletti a) Verilog HDL source code
Verilog-HDL-design-
- verilog设计流程学习,帮助我们快速学习verilog代码-the verilog design process learning, we quickly learn verilog code
Advance-HDL-Design-Training-On-Xilinx-FPGA
- dvance HDL Design Training On XilinxFPGA thanhmaikmt dao thanh mai
《Verilog HDL设计与实战》配套代码(1)
- 《Verilog HDL设计与实战》配套代码 verilog源程序(Verilog HDL design and actual combat code Verilog source program)
《Verilog HDL设计与实战》配套代码(2)
- 《Verilog HDL设计与实战》配套代码 (2)("Verilog HDL design and actual combat" matching code (2))