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uart_rx
- actel A3P250 fpga用VERILOG HDL语言实现串口功能的源代码
UART_send
- Verilog HDL 串口发送程序，在ACTEL Fusion FPGA上实验成功 ，和大家一起分享！^_^
dual_RAM.rar
- actel fusion startkit FPGA开发板试验例程，可实现2k8的双口ram，实现数据存储，缓冲。包含verilog HDL 语言源码,actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog
my_and
- 此实验例程适用于Actel Flash架构的ProASIC3/E系列FPGA，适合于FPGA及Verilog HDL的初学者，配套EasyFPGA030开发套件。-Routine application of this experiment in the Actel Flash architecture ProASIC3/E series FPGA, fit in the FPGA and Verilog HDL for beginners and supporting development
hdl
- 用Actel公司的Fusion系列FPGA开发的LCD实验程序-Fusion with Actel s FPGA development series LCD Experimental procedures
hdlcode_ug
- Verilog HDL Coding Guidelines - ACTEL -Verilog HDL Coding Guidelines- ACTEL
111
- Verilog语言编写的循环彩灯控制器 这个程序我已经在Actel板上烧过了，没问题。如果还有什么问题应该是你的板不同或者工具不同，我是在libero_8.5上做的 -VeriloG HDL IS VEVRY USEFUL
hdl
- ACTEL串口收发 Verilog语言描述-ACTEL serial port transceiver
hdl
- ACTEL FPGA 1602显示，verilog描述-ACTEL FPGA 1602 show, verilog descr iption
hdl
- ACTEL FPGA 交通灯，Verilog描述-ACTEL FPGA traffic lights, Verilog descr iption
hdl
- ACTEL FPGA 6位数码管计数999999，Verilog描述-ACTEL FPGA 6 bits digital tube count 999999, Verilog descr iption
RTC
- actel fpga开发板fusion startkit实验例程，包含完整工程文件几verilog HDL 源码-actel fpga development board fusion startkit test routines, including the complete works of several verilog HDL source file
74hc4017
- 实现的是扭环形十进制计数器，用verilog HDL 语言，在Actel公司提供的LiberoFPGA开发环境下实现，代码经过验证，可在ModelSim中仿真 -Ring is twisted to achieve a decimal counter, using verilog HDL language, Actel offers the LiberoFPGA development environment, the code is validated, the simulation in t
hdl
- actel单片机的软FIFO设计和串口通讯程序-actel single chip design soft FIFO and serial communication program
ACtel-RTC-hdl
- 基于Actel公司的反熔丝FPGA实现，实现了实时时钟功能。能区分闰年、大月、小月，秒、分、时自动增长。-this application provides a count of seconds, minutes, hours, day of the week, day of the month, month, and year. The month-ending date is automatically adjusted for months with less than
三角函数的Verilog HDL语言实现
- 以Actel FPGA作为控制核心，通过自然采样法比较1个三角载波和3个相位差为1 200的正弦波，利用Verilog HDL语言实现死区时间可调的SPWM全数字算法，并在Fushion StartKit开发板上实现SPWM全数字算法。(With Actel FPGA as the control core, between 1 and 3 triangular carrier phase difference of 1200 sine wave by natural sampling, rea