搜索资源列表
ARM_Core
- arm verilog hdl ip core-arm Verilog HDL core ip
ip
- 15个免费的ip核包含avr core，core arm核
ARMcore
- 基于FPGA的ARM IP核！该软核VHDL源码全部开放-FPGA-based ARM IP core! The soft core VHDL source code are all open
BaselineJPEGSoftwareCodecCodes
- In term project, we will take the baseline JPEG codec in ARM-based platform system as an example to practice the design flow in SoC. We divide the project into three parts, and the goal of each part is described as follow. Part I: Design a baseli
vhdl-arm-core
- 用vhdl语言实现arm内核，压缩包中有19个代码共同组成这个arm内核，程序比较大，应用时要注意那个代码是顶层实体。用quartus2软件即可打开仿真。-Vhdl language used arm core, compressed package code of 19 common core component of this arm, procedures, and application code should be noted that top-level entity. Used t
core_arm
- 从opencore找都的ARM的IP CORE。有详细说明。-From opencore to find all of the ARM' s IP CORE. Is described in detail.
arm7verilog
- ARM 7 免费ip 核， verilog语言描述-arm7 free ip core, verilig DHL
12130_ARM_Core
- arm 核，VHDL语言描述的IP软核，仅供学习-arm-core, VHDL language to describe the IP soft core, only to learn
ThesummaryofSoCOCB
- 随着以IP核复用为基础的SoC设计技术的发展，工业界及研究组织积极从事相关IP互联标准 方案的制定工作，从目前的研究和发展看，影响力较大的有IBM 公司的CoreConnect、ARM 公司的AMBA 和Silicore Corp公司的Wishbone。基于现有IP互联接口标准技术的发展现状，本文对这三种SoC总线技 术进行了详细介绍。-Along with the IP core reuse-based SoC design technology, industry and res
illinoi_arm7
- 一种ARM IP core，国外一个论坛上载下来的，希望能有所用处-A ARM IP core, a forum set off abroad, and hope to be useful
acoral
- acoral是一个操作系统，aCoral支持多线程模式，其最小配置时，生成的代码为7K左右，而配置文件系统，轻型TCP/IP，GUI后生成的代码仅有300K左右。目前，aCoral支持各种ARM系列处理器：Cortex-m3, ARM7, ARM9，ARM11，以及ARM11MPCORE四核平台(链接)。同时，为了方便没有开发板的用户体验aCoral，其模拟版本可以在运行Linux的PC中作为应用程序运行，这种模式可以体验aCoral的所有功能，包括内核、文件系统、GUI，该模式支持单核和多核-
ARM-Verilog-HDL-IP-CORE
- ARM Verilog HDL IP CORE
network-video--player
- 提供的代码是编写一个基于linux系统的网络视频点播应用程序，利用Qt工具编写图形界面和基于TCP协议的网络传输模块。Linux操作系统以其开源性、多用户多任务、支持多种硬件平台、可靠地安全稳定性能以及日趋完善的图形界面和丰富的网络功能等等，逐渐成为了各行业的首选操作系统，尤其是基于ARM内核的嵌入式linux更是得到了极为广泛的应用。 本系统分为服务器端和客户端两部分。服务器端提供多视频源，供用户进行选择，客户端提供人机交互界面，当用户需要点播某个视频时，首先在Ip Address栏输
ARMCORE
- arm7的内核，包括arm ip代码和仿真结果-ARM7 core,include arm code and simulation result
ARM-Verilog-HDL-IP-CORE
- ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。-ARM processor IP core, written in verilog processor and CPU architecture knowledge.
ARM-Verilog-HDL-IP-CORE
- ARM Verilog HDL IP CORE， ARM IP核，采用verilog编写-ARM Verilog HDL IP CORE, ARM IP core, using verilog write
rtl_1795
- Developper:mathswork Arm IP Core Verilog This IP core is an ARM clone. It has the same architecture of ARM v4. Its main feature lists: Not support coprocessor instructions Not support THUMB instruction set All interrupts
SARM7TM
- ARM ip核设计 其中设计了ARM7的各个功能模块，具体模块有很多个-ARM ip core
axi_ipif_v2.3
- The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point
Can总线协议-立方体卫星空间协议（源代码）
- Can总线协议-立方体卫星空间协议（源代码） The Cubesat Space Protocol Cubesat Space Protocol (CSP) is a small protocol stack written in C. CSP is designed to ease communication between distributed embedded systems in smaller networks, such as Cubesats. The design